IP Library › Granted Patent US 12676181
Granted Patent B2
US 12676181 · App. 18/772,117 · Granted Jul 7, 2026

Memory circuits, memory structures, and methods for fabricating a memory device

Inventors: Chieh Lee (Hsinchu, TW); Yi-Ching Liu (Hsinchu, TW); Chia-En Huang (Xinfeng Township, TW); Wen-Chang Cheng (Richmond, TX); Jonathan Tsung-Yung Chang (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
G11C11/4091H10B12/09H10B12/50
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Quick Facts
Patent No.
US 12676181
App. No.
18/772,117
Granted
Jul 7, 2026
Kind
B2
Abstract

A memory structure includes a first memory array having bit lines; a second memory array having bit lines; a first sense amplifier connected to a first bit line of the first memory array and a first bit line of the second memory array; and a second sense amplifier connected to a second bit line of the first memory array and a second bit line of the second memory array. The second bit line of the first memory array is adjacent to the first bit line of the first memory array, and the second bit line of the second memory array is adjacent to the first bit line of the second memory array.

Claims (40)

1 . A circuit, comprising:

a first sense amplifier connected to a first bit line of a first memory array and a first bit line of a second memory array, wherein the first bit line of the first memory array is displaced from the first bit line of the second memory array by a half pitch; and

a second sense amplifier connected to a second bit line of the first memory array and a second bit line of the second memory array.

2 . The circuit of claim 1 , wherein the first sense amplifier receives a first differential voltage on the first bit line of the first memory array, and the first bit line of the second memory array remains at a reference voltage.

3 . The circuit of claim 1 , wherein the first sense amplifier and the second sense amplifier are bit line sense amplifiers.

4 . The circuit of claim 1 , wherein the first sense amplifier comprises a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor, the second NMOS transistor and the third NMOS transistor are coupled in series between the first bit line of the first memory array and the first bit line of the second memory array, and the first NMOS transistor is connected between an internal ground voltage node and a source terminal of the second NMOS transistor and a source terminal of the third NMOS transistor.

5 . The circuit of claim 4 , wherein the first sense amplifier further comprises a first PMOS transistor, a second PMOS transistor, and a third PMOS transistor, the first PMOS transistor and the second PMOS transistor are coupled in series between the first bit line of the first memory array and the first bit line of the second memory array, and the third PMOS transistor is connected between a power supply voltage node and a source terminal of the first PMOS transistor and a source terminal of the second PMOS transistor.

6 . The circuit of claim 1 , wherein the second sense amplifier comprises a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor, the second NMOS transistor of the second sense amplifier and the third NMOS transistor of the second sense amplifier are coupled in series between the second bit line of the first memory array and the second bit line of the second memory array, and the first NMOS transistor of the second sense amplifier is connected between an internal ground voltage node and a source terminal of the second NMOS transistor of the second sense amplifier and a source terminal of the third NMOS transistor of the second sense amplifier.

7 . The circuit of claim 6 , wherein the second sense amplifier further comprises a first PMOS transistor, a second PMOS transistor, and a third PMOS transistor, the first PMOS transistor of the second sense amplifier and the second PMOS transistor of the second sense amplifier are coupled in series between the second bit line of the first memory array and the second bit line of the second memory array, and the third PMOS transistor of the second sense amplifier is connected between the power supply voltage node and a source terminal of the first PMOS transistor of the second sense amplifier and a source terminal of the second PMOS transistor of the second sense amplifier.

8 . The circuit of claim 1 , wherein the first sense amplifier and the second sense amplifier are located within a front-end-of-line (FEOL) structure of the circuit.

9 . The circuit of claim 1 , wherein the first sense amplifier and the second sense amplifier are located within the same front-end-of-line (FEOL) region under the first memory array or the second memory array.

10 . The circuit of claim 1 , further comprising:

a third sense amplifier connected to a third bit line of the first memory array and a third bit line of the second memory array; and

a fourth sense amplifier connected to a fourth bit line of the first memory array and a fourth bit line of the second memory array;

wherein the first sense amplifier and the second sense amplifier are located within a first front-end-of-line (FEOL) region under the first memory array, and the third sense amplifier and the fourth sense amplifier are located within a second front-end-of-line (FEOL) region under the second memory array.

11 . A circuit structure, comprising:

a front-end-of-line (FEOL) periphery circuitry, comprising:

a first sense amplifier circuit; and

a second sense amplifier circuit;

a first back-end-of-line (BEOL) memory array disposed over the FEOL periphery circuitry;

a second BEOL memory array disposed over the FEOL periphery circuitry;

a plurality of conducting layers disposed between the FEOL periphery circuitry and the first BEOL memory array and the second BEOL memory array over the FEOL periphery circuitry;

wherein the plurality of conducting layers connect a first bit line of the first memory array and a first bit line of the second memory array to the first sense amplifier circuit;

wherein the plurality of conducting layers connect a second bit line of the first memory array and a second bit line of the second memory array to the second sense amplifier circuit; and

wherein the first bit line of the first memory array has an offset with respect to the first bit line of the second memory array, and the second bit line of the first memory array has an offset with respect to the second bit line of the second memory array.

12 . The circuit structure of claim 11 , wherein the first sense amplifier circuit is located within a first region of the FEOL periphery circuitry under the first memory array, and the second sense amplifier circuit is located within a second region of the FEOL periphery circuitry under the second memory array.

13 . The circuit structure of claim 11 , wherein the first sense amplifier circuit is located within a region of the FEOL periphery circuitry under the first memory array, and the second sense amplifier circuit is located within a region of the FEOL periphery circuitry under the second memory array.

14 . The circuit structure of claim 11 , wherein each of the plurality of conducting layers comprises a plurality of conducting features, and the plurality of conducting layers are connected to each other via the conducting features.

15 . The circuit structure of claim 11 , wherein the first bit line of the first memory array is displaced from the first bit line of the second memory array by a half pitch, and the second bit line of the first memory array is displaced from the second bit line of the second memory array by a half pitch.

16 . The circuit structure of claim 11 , wherein the first bit line of the first memory array is adjacent to the first bit line of the second memory array, and the second bit line of the first memory array is adjacent to the second bit line of the second memory array.

17 . The circuit structure of claim 16 , wherein the first sense amplifier circuit and the second sense amplifier circuit are placed in a same row in the FEOL periphery circuitry.

18 . A method for fabricating a memory device, comprising:

forming a periphery circuit, including a first sense amplifier circuit and a second sense amplifier circuit, over a substrate layer;

forming a plurality of conducting layers over the periphery circuitry;

forming a first memory array and a second memory array over the plurality of conducting layers; and

forming a plurality of bit lines of the first memory array and a plurality of bit lines of the second memory array;

wherein the bit lines of the first memory array are displaced from the bit lines of the second memory array by an offset;

wherein the conducting layers are disposed between the periphery circuitry and the first memory array or the second memory array, to connect a first bit line pair to the first sense amplifier circuit and to connect a second bit line pair to the second sense amplifier circuit, the second bit line pair being adjacent to the first bit line pair.

19 . The method of claim 18 , wherein the offset is equal to 0.

20 . The method of claim 18 , wherein the offset is equal to a half pitch.