IP Library › Granted Patent US 12676182
Granted Patent B2
US 12676182 · App. 18/778,336 · Granted Jul 7, 2026

Bit line pre-charge voltage generating circuit in semiconductor memory devices for reducing current consumption

Inventor: Jae Jin Lee (Gwangju-si, KR)
Assignee: FIDELIX CO., LTD.
G11C11/4094G11C11/4099H03K19/01721H03K19/20
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Quick Facts
Patent No.
US 12676182
App. No.
18/778,336
Granted
Jul 7, 2026
Kind
B2
Abstract

A bit line pre-charge voltage generating circuit in a semiconductor memory device may reduce current consumption. The bit line pre-charge voltage generating circuit includes a reference voltage generating portion that generates a pull-down reference voltage and a pull-up reference voltage; a comparing portion that generates a pull-up comparison signal by comparing the level of the bit line pre-charge voltage with that of the pull-up reference voltage, and generates a pull-down comparison signal by comparing the level of the bit line pre-charge voltage with that of the pull-down reference voltage; a driving portion that includes a pull-up driving element and a pull-down driving element; and an activation overlap reduction portion that generates the pull-up control signal and the pull-down control signal The activation overlap reduction portion can minimize the overlap between the turn-on sections of the pull-up driving element and the pull-down driving element of the driving portion.

Claims (56)

1 . A bit line pre-charge voltage generating circuit in a semiconductor memory device that generates a bit line pre-charge voltage, comprising:

a reference voltage generating portion that generates a pull-down reference voltage and a pull-up reference voltage, the level of the pull-down reference voltage being higher than that of the pull-up reference voltage;

a comparing portion that generates a pull-up comparison signal by comparing the level of the bit line pre-charge voltage with that of the pull-up reference voltage, and generates a pull-down comparison signal by comparing the level of the bit line pre-charge voltage with that of the pull-down reference voltage, the pull-up comparison signal being activated as the level of the bit line pre-charge voltage is lower than that of the pull-up reference voltage, and the pull-down comparison signal being activated as the level of the bit line pre-charge voltage is higher than that of the pull-up reference voltage;

a driving portion that includes a pull-up driving element and a pull-down driving element, the pull-up driving element being formed between a core voltage and the bit line pre-charge voltage, and being driven to increase the level of the bit line pre-charge voltage according to activation of the pull-up control signal, and the pull-down driving element being formed between a ground voltage and the bit line pre-charge voltage, and being driven to decrease the level of the bit line pre-charge voltage according to activation of the pull-down control signal; and

an activation overlap reduction portion that generates the pull-up control signal and the pull-down control signal by performing a logical operation on the pull-up comparison signal and the pull-down comparison signal, wherein

the pull-up control signal is activated according to activation of the pull-up comparison signal in a deactivated state of the pull-down comparison signal, and is controlled to be deactivated according to activation of the pull-down comparison signal, and

the pull-down control signal is activated according to activation of the pull-down comparison signal in a deactivated state of the pull-up comparison signal, and is controlled to be deactivated according to activation of the pull-up comparison signal.

2 . The bit line pre-charge voltage generating circuit of claim 1 , wherein the reference voltage generating portion includes:

a first resistance element formed between the core voltage and the pull-down reference voltage;

a second resistance element formed between the pull-down reference voltage and the pull-up reference voltage; and

a third resistance element formed between the pull-up reference voltage and the ground voltage.

3 . The bit line pre-charge voltage generating circuit of claim 1 , wherein the comparing portion includes:

a pull-up comparator that is driven to generate the pull-up comparison signal by comparing the level of the bit line pre-charge voltage with that of the pull-up reference voltage; and

a pull-down comparator that is driven to generate the pull-down comparison signal by comparing the level of the bit line pre-charge voltage with that of the pull-down reference voltage.

4 . The bit line pre-charge voltage generating circuit of claim 1 , wherein

the pull-up driving element is a PMOS transistor formed between the core voltage and the bit line pre-charge voltage and gated on the pull-up control signal, and

the pull-down driving element is a NMOS transistor formed between the ground voltage and the bit line pre-charge voltage and gated on the pull-down control signal.

5 . The bit line pre-charge voltage generating circuit of claim 1 , wherein the activation overlap reduction portion includes:

an OR unit for generating the pull-up control signal by performing an OR operation on the pull-up comparison signal and the pull-down comparison signal; and

an AND unit for generating the pull-down control signal by performing an AND operation on the pull-up comparison signal and the pull-down comparison signal.

6 . A bit line pre-charge voltage generating circuit in a semiconductor memory device that generates a bit line pre-charge voltage, comprising:

a reference voltage generating portion that generates a pull-down reference voltage and a pull-up reference voltage, the level of the pull-down reference voltage being higher than that of the pull-up reference voltage;

a comparing portion that generates a pull-up comparison signal by comparing the level of the bit line pre-charge voltage with that of the pull-up reference voltage, and generates a pull-down comparison signal by comparing the level of the bit line pre-charge voltage with that of the pull-down reference voltage, the pull-up comparison signal being activated as the level of the bit line pre-charge voltage is lower than that of the pull-up reference voltage, and the pull-down comparison signal being activated as the level of the bit line pre-charge voltage is higher than that of the pull-up reference voltage;

a driving portion that includes a pull-up driving element and a pull-down driving element, the pull-up driving element being formed between a core voltage and the bit line pre-charge voltage, and being driven to increase the level of the bit line pre-charge voltage according to activation of the pull-up control signal, and the pull-down driving element being formed between a ground voltage and the bit line pre-charge voltage, and being driven to decrease the level of the bit line pre-charge voltage according to activation of the pull-down control signal; and

an activation overlap reduction portion that generates the pull-up control signal and the pull-down control signal with receiving the pull-up comparison signal and the pull-down comparison signal, wherein

the pull-up control signal is activated according to activation of the pull-up comparison signal in a deactivated state of the pull-down comparison signal, and remains in an inactive state despite of the activation of the pull-up comparison signal in case that the pull-down comparison signal is activated, and

the pull-down control signal is activated according to activation of the pull-down comparison signal in a deactivated state of the pull-up comparison signal, and remains in an inactive state despite of the activation of the pull-down comparison signal in case that the pull-up comparison signal is activated.

7 . The bit line pre-charge voltage generating circuit of claim 6 , wherein the reference voltage generating portion includes:

a first resistance element formed between the core voltage and the pull-down reference voltage;

a second resistance element formed between the pull-down reference voltage and the pull-up reference voltage; and

a third resistance element formed between the pull-up reference voltage and the ground voltage.

8 . The bit line pre-charge voltage generating circuit of claim 6 , wherein the comparing portion includes:

a pull-up comparator that is driven to generate the pull-up comparison signal by comparing the level of the bit line pre-charge voltage with that of the pull-up reference voltage; and

a pull-down comparator that is driven to generate the pull-down comparison signal by comparing the level of the bit line pre-charge voltage with that of the pull-down reference voltage.

9 . The bit line pre-charge voltage generating circuit of claim 6 , wherein

the pull-up driving element is a PMOS transistor formed between the core voltage and the bit line pre-charge voltage and gated on the pull-up control signal, and

the pull-down driving element is a NMOS transistor formed between the ground voltage and the bit line pre-charge voltage and gated on the pull-down control signal.

10 . The bit line pre-charge voltage generating circuit of claim 6 , wherein the activation overlap reduction portion includes:

a pull-up blocking latch unit for receiving the pull-up comparison signal and the pull-down comparison signal and generating the pull-up control signal, the pull-up control signal being activated according to activation of the pull-up comparison signal in a deactivated state of the pull-down comparison signal, and being latched in an inactive state despite of the activation of the pull-up comparison signal in case that the pull-down comparison signal is in an activate state, and the latch of the pull-up control signal being released in response to deactivation of the pull-down comparison signal; and

a pull-down blocking latch unit for receiving the pull-up comparison signal and the pull-down comparison signal and generating the pull-down control signal, the pull-down control signal being activated according to activation of the pull-down comparison signal in a deactivated state of the pull-up comparison signal, and being latched in an inactive state despite of the activation of the pull-down comparison signal in case that the pull-up comparison signal is in an activate state, and the latch of the pull-down control signal being released in response to deactivation of the pull-up comparison signal.

11 . A semiconductor memory device, comprising:

a bit line pre-charge voltage generating circuit that generates a bit line pre-charge voltage, including:

a reference voltage generating portion that generates a pull-down reference voltage and a pull-up reference voltage, the level of the pull-down reference voltage being higher than that of the pull-up reference voltage;

a comparing portion that generates a pull-up comparison signal by comparing the level of the bit line pre-charge voltage with that of the pull-up reference voltage, and generates a pull-down comparison signal by comparing the level of the bit line pre-charge voltage with that of the pull-down reference voltage, the pull-up comparison signal being activated as the level of the bit line pre-charge voltage is lower than that of the pull-up reference voltage, and the pull-down comparison signal being activated as the level of the bit line pre-charge voltage is higher than that of the pull-up reference voltage;

a driving portion that includes a pull-up driving element and a pull-down driving element, the pull-up driving element being formed between a core voltage and the bit line pre-charge voltage, and being driven to increase the level of the bit line pre-charge voltage according to activation of the pull-up control signal, the pull-down driving element being formed between a ground voltage and the bit line pre-charge voltage, and being driven to decrease the level of the bit line pre-charge voltage according to activation of the pull-down control signal, and

an activation overlap reduction portion that generates the pull-up control signal and the pull-down control signal, wherein

the pull-up control signal is activated according to activation of the pull-up comparison signal in a deactivated state of the pull-down comparison signal, and

the pull-down control signal is activated according to activation of the pull-down comparison signal in a deactivated state of the pull-up comparison signal.

12 . The semiconductor memory device of claim 11 , wherein

the activation overlap reduction portion generates the pull-up control signal and the pull-down control signal by performing a logical operation on the pull-up comparison signal and the pull-down comparison signal,

the pull-up control signal is controlled to be deactivated according to activation of the pull-down comparison signal, and

the pull-down control signal is controlled to be deactivated according to activation of the pull-up comparison signal.

13 . The semiconductor memory device of claim 11 , wherein

the activation overlap reduction portion generates the pull-up control signal and the pull-down control signal with receiving the pull-up comparison signal and the pull-down comparison signal,

the pull-up control signal remains in an inactive state despite of the activation of the pull-up comparison signal in case that the pull-down comparison signal is activated, and

the pull-down control signal remains in an inactive state despite the activation of the pull-down comparison signal in case that the pull-up comparison signal is activated.