Semiconductor memory cell having two gates and one channel layer
View Patent ↗In a semiconductor memory device, an n-type semiconductor layer is formed on a p-type semiconductor region on a substrate, a p-type first semiconductor layer having a columnar shape and concave top surface extends vertically from part of the n-type semiconductor layer, the p-type first semiconductor layer and n-type semiconductor layer are partially covered with an insulating layer, a first gate insulating layer is placed in contact with the p-type first semiconductor layer, a first gate conductor layer is placed in contact with the first gate insulating layer, and a second gate insulating layer, a second gate conductor layer, and an access transistor with an n+ layer provided on both sides are installed along a surface of the p-type first semiconductor layer.
1 . A semiconductor memory cell comprising:
a first semiconductor region;
a first impurity region formed on the first semiconductor region;
a second semiconductor region formed in a vertical direction in contact with the first impurity region, wherein the second semiconductor region is formed to have a recess in its top surface;
a first gate insulating layer formed to surround part of the second semiconductor region;
a first gate conductor layer formed in contact with the first gate insulating layer;
a second gate insulating layer formed along an interior surface of the recess of the second semiconductor region, wherein the second gate insulating layer is formed to have a second recess in its top surface;
a second gate conductor layer formed inside the second recess of the second gate insulating layer; and
a second impurity region and a third impurity region formed separately in contact with the top surface of the second semiconductor region,
wherein the second gate conductor layer has a top surface located lower than top surfaces of the second impurity region and the third impurity region, and
further wherein a charge type of majority carriers in the second semiconductor region is identical to a charge type of majority carriers in the first semiconductor region.
2 . The semiconductor memory cell according to claim 1 , wherein the second impurity region and the third impurity region are formed in contact with the second gate insulating layer.
3 . The semiconductor memory cell according to claim 1 , wherein one or both of (i) a contact surface between the second semiconductor region and the second impurity region and (ii) a contact surface between the second semiconductor region and the third impurity region are located higher than a bottom of the second gate insulating layer.
4 . The semiconductor memory cell according to claim 1 , further comprising an insulating layer formed between the second impurity region and the third impurity region.
5 . The semiconductor memory cell according to claim 1 , wherein a minimum distance between the second impurity region and the third impurity region is larger than a horizontal length of a vertical section of the second gate conductor layer.
6 . The semiconductor memory cell according to claim 1 , wherein a charge type of majority carriers in the first impurity region is different from a charge type of majority carriers in the first semiconductor region.
7 . The semiconductor memory cell according to claim 1 , wherein a charge type of majority carriers in the second impurity region and the third impurity region is identical to a charge type of majority carriers in the first impurity region.
8 . The semiconductor memory cell according to claim 1 , wherein the first impurity region is shared by a plurality of adjacent memory cells.
9 . The semiconductor memory cell according to claim 1 , wherein the second impurity region or the third impurity region is shared by a plurality of adjacent memory cells.
10 . The semiconductor memory cell according to claim 1 , wherein a top surface of the first impurity region is formed higher than a lower surface of the first gate insulating layer.
11 . The semiconductor memory cell according to claim 1 , wherein lower surfaces of the second impurity region and the third impurity region are formed higher than a top surface of the first gate insulating layer.
12 . The semiconductor memory cell according to claim 1 , wherein a threshold of a MOS transistor made up of the second semiconductor region, the second impurity region, the third impurity region, the second gate insulating layer, and the second gate conductor layer is varied by changing a voltage applied to the first gate conductor layer.
13 . The semiconductor memory cell according to claim 1 , further comprising:
a first interconnecting conductor layer connected to the second impurity region;
a second interconnecting conductor layer connected to the third impurity region;
a third interconnecting conductor layer connected to the second gate conductor layer;
a fourth interconnecting conductor layer connected to the first gate conductor layer; and
a fifth interconnecting conductor layer connected to the first impurity region,
wherein a memory write operation is performed by controlling voltages applied to the first interconnecting conductor layer, the second interconnecting conductor layer, the third interconnecting conductor layer, the fourth interconnecting conductor layer, and the fifth interconnecting conductor layer and performing an operation of generating electron groups and positive hole groups in the second semiconductor region, by an impact ionization phenomenon or a gate induced drain leakage current using a current passed between the second impurity region and the third impurity region, an operation of removing minority carriers in the second semiconductor region among the generated electron groups and the positive hole groups, and an operation of causing part or all of majority carriers in the second semiconductor region to remain in the second semiconductor region, and
a memory erase operation is performed by controlling voltages applied to the first interconnecting conductor layer, the second interconnecting conductor layer, the third interconnecting conductor layer, the fourth interconnecting conductor layer, and the fifth interconnecting conductor layer and extracting majority carriers remaining in the second semiconductor region from at least one of the first impurity region, the second impurity region, and the third impurity region by recombining the majority carriers with majority carriers in the first impurity region, the second impurity region, and the third impurity region.
14 . The semiconductor memory cell according to claim 13 , wherein:
the first interconnecting conductor layer connected to the second impurity region is a source line;
the second interconnecting conductor layer connected to the third impurity region is a bit line,
the third interconnecting conductor layer connected to the second gate conductor layer is a word line;
the fourth interconnecting conductor layer connected to the first gate conductor layer is a plate line;
the fifth interconnecting conductor layer is a control line; and
the memory write operation and the memory erase operation are performed by applying voltages to the source line, the bit line, the plate line, the word line, and the control line.