Voltage regulator, memory device including voltage regulator, and operation method of memory device

1 . A memory device comprising:

a reference voltage generator configured to generate a reference voltage;

a voltage regulator including a plurality of driving blocks configured to generate an internal voltage based on the reference voltage;

a power line configured to receive the internal voltage; and

a regulator control circuit configured to enable the plurality of driving blocks,

wherein at least one of the plurality of driving blocks includes:

a first unit driver configured to generate a first output current flowing through the power line based on the reference voltage and a change in the internal voltage; and

a second unit driver configured to generate a second output current larger than the first output current flowing through the power line, based on the reference voltage and the change in the internal voltage,

wherein the first unit driver is configured to generate the first output current faster than the second output current of the second unit driver,

wherein the regulator control circuit is further configured to:

enable n driving blocks among the plurality of driving blocks, n being a natural number, when a load current flowing to the power line increases from a first value to a second value, and

disable first unit drivers included in each of the n driving blocks when the load current is maintained at the second value.

2 . The memory device of claim 1 , wherein the first unit driver includes:

a first amplifier configured to output a first comparison signal based on a difference between the reference voltage and the internal voltage; and

a first pass transistor connected between an external voltage and the power line, and configured to generate the first output current flowing through the power line in response to the first comparison signal,

wherein the second unit driver includes:

a second amplifier configured to output a second comparison signal based on the difference between the reference voltage and the internal voltage; and

a second pass transistor connected between the external voltage and the power line, and configured to generate the second output current flowing through the power line in response to the second comparison signal,

wherein a size of the first amplifier is identical to a size of the second amplifier, and

wherein a size of the second pass transistor is larger than a size of the first pass transistor.

3 . The memory device of claim 2 , wherein the first unit driver further includes a first capacitor connected between the power line and an output terminal of the first amplifier,

wherein the second unit driver further includes a second capacitor connected between the power line and an output terminal of second first amplifier, and

wherein a first ratio of the first capacitor and the second capacitor is proportional to a second ratio of the size of the first pass transistor and the size of the second pass transistor.

4 . The memory device of claim 2 , wherein the at least one of the plurality of driving blocks further includes:

a third unit driver configured to generate a third output current larger than the first output current and smaller than the second output current flowing through the power line, based on the reference voltage and the change in the internal voltage.

5 . The memory device of claim 4 , wherein the third unit driver includes:

a third amplifier configured to output a third comparison signal based on the difference between the reference voltage and the internal voltage; and

a third pass transistor connected between the external voltage and the power line, and configured to generate the third output current flowing through the power line in response to the third comparison signal,

wherein a size of the third amplifier is identical to the size of the first amplifier and the size of the second amplifier, and

wherein a size of the third pass transistor is larger than the size of the first pass transistor and is smaller than the size of the second pass transistor.

6 . The memory device of claim 1 ,

wherein the regulator control circuit is further configured to enable m driving blocks among the plurality of driving blocks, m being a natural number greater than n, when the load current flowing through the power line increases from the second value to a third value.

7 . The memory device of claim 1 , further comprising:

an input/output circuit applying the internal voltage and configured to transmit/receive data to/from an external device.

8 . The memory device of claim 7 , wherein the regulator control circuit is further configured to:

enable the first unit driver and the second unit driver, at a time point when the input/output circuit starts to transmit/receive the data to/from the external device, and

disable the first unit driver, while the input/output circuit transmits/receives the data to/from the external device.

9 . The memory device of claim 1 , further comprising:

a standby driver configured to provide the internal voltage to the power line during an idle period of the memory device.

10 . The memory device of claim 1 , wherein each of remaining driving blocks other than the at least one driving block includes:

a single unit driver connected to the power line, and configured to generate a third output current different from the first output current and the second output current flowing through the power line.

11 . The memory device of claim 10 , further comprising:

a substrate including a first area and a second area spaced from the first area as much as a given distance; and

a plurality of pins disposed in the first area and configured to exchange signals with an external device,

wherein the at least one of the plurality of driving blocks is formed in the first area, and

wherein the remaining driving blocks are formed in second area.

12 . The memory device of claim 1 , further comprising:

a memory cell array including a plurality of memory cells;

an address decoder connected to the memory cell array through a plurality of word lines;

a page buffer circuit connected to the memory cell array through a plurality of bit lines;

an input/output circuit connected to the page buffer circuit; and

a control logic circuit configured to control the address decoder, the page buffer circuit, and the input/output circuit.

13 . The memory device of claim 12 , wherein at least one of the memory cell array, the address decoder, the page buffer circuit, the input/output circuit, and the control logic circuit is:

connected to the power line, and

configured to operate based on the internal voltage provided through the power line.

14 . An operation method of a memory device which includes a plurality of driving blocks configured to output an internal voltage to a power line, the method comprising:

enabling n driving blocks among the plurality of driving blocks, in a first operating period in which a first load current is used, n being a natural number;

enabling m driving blocks among the plurality of driving blocks, in a second operating period in which a second load current larger than the first load current is used, m being a natural number greater than n; and

when the second load current is maintained at a target level disabling a first unit driver included in each of the m driving blocks,

wherein the enabling of the n driving blocks includes:

by a first unit driver of at least one of the plurality of driving blocks, generating a first output current flowing through the power line based on a reference voltage and a change in the internal voltage; and

by a second unit driver of the at least one of the plurality of driving blocks, generating a second output current larger than the first output current flowing through the power line based on the reference voltage and the change in the internal voltage, and

wherein the generating of the first output current occurs faster than the generating of the second output current.

15 . The method of claim 14 , wherein the second operating period is a period in which the memory device transmits/receives data to/from an external device.

16 . A memory device comprising:

a reference voltage generator configured to generate a reference voltage;

a voltage regulator including a plurality of driving blocks configured to generate an internal voltage based on the reference voltage; and

a power line configured to receive the internal voltage,

wherein at least one of the plurality of driving blocks includes:

a first unit driver configured to generate a first output current flowing through the power line based on the reference voltage and a change in the internal voltage; and

a second unit driver configured to generate a second output current larger than the first output current flowing through the power line, based on the reference voltage and the change in the internal voltage,

wherein the first unit driver is configured to generate the first output current faster than the second output current of the second unit driver,

wherein one of remaining driving blocks other than the at least one of the plurality of driving blocks includes:

a single unit driver connected to the power line, and configured to generate a third output current different from the first output current and the second output current flowing through the power line, and

wherein the first, second, and third output currents are combined into the power line.