Memory device

1 . A device, comprising:

a substrate having a front side and a back side opposite the front side;

an interconnect structure situated on or over the substrate, the interconnect structure including first and second metal layers and a via electrically connecting the first and second metal layers; and

a word line driver circuit configured to output a word line enable signal to a word line of a memory array, the word line driver circuit including:

an inverter circuit configured to receive a word line signal, wherein the inverter circuit includes a first PMOS transistor and a first NMOS transistor, and wherein the output of the inverter circuit is formed at a junction of the first PMOS transistor and the first NMOS transistor; and

an enable transistor electrically connected to an output of the inverter circuit by a metal line that includes the first metal layer, the second metal layer, and the via, wherein the enable transistor includes a second PMOS transistor, and wherein the enable transistor is a FinFET.

2 . The device of claim 1 , wherein the FinFET includes fewer than 10 gate fingers.

3 . The device of claim 1 , wherein the FinFET includes 7 gate fingers.

4 . The device of claim 1 , wherein the metal line has a resistance greater than 200 ohms.

5 . The device of claim 1 , wherein the metal line has a resistance of 200 to 400 ohms.

6 . The device of claim 1 , wherein the interconnect structure includes a front side interconnect structure situated on or over the front side of the substrate, a back side interconnect structure situated on or over the back side of the substrate, and an interlayer via extending through the substrate and electrically connecting the front side interconnect structure and the back side interconnect structure, and wherein the metal line includes the front side interconnect structure, the back side interconnect structure and the interlayer via.

7 . The device of claim 6 , further comprising first and second tiers, wherein at least one of the first PMOS transistor, the first NMOS transistor and/or the second PMOS transistor are in the first tier, and wherein at least one of the first PMOS transistor, the first NMOS transistor and/or the second PMOS transistor are in the second tier.

8 . A memory device, comprising:

a memory array including a plurality of memory cells arranged in rows and columns, wherein the memory cells are SRAM cells;

a plurality of word lines connected to the memory cells of respective rows of the memory array;

a word line driver circuit configured to output word line enable signals to respective word lines, the word line driver circuit including:

a substrate;

an interconnect structure situated on or over the substrate, wherein the interconnect structure includes a front side interconnect structure situated on or over a front side of the substrate, a back side interconnect structure situated on or over a back side of the substrate opposite the front side, and an interlayer via extending through the substrate and electrically connecting the front side interconnect structure and the back side interconnect structure;

a plurality of inverter circuits and a plurality of enable transistors electrically connected to respective ones of the word lines by metal lines of the interconnect structure, wherein:

the inverter circuits each include a first PMOS transistor and a first NMOS transistor;

the enable transistors each include a second PMOS transistor;

an output of the inverter circuit is formed at a junction of the first PMOS transistor and the first NMOS transistor;

wherein at least one of the first PMOS transistor, the first NMOS transistor and/or the second PMOS transistor are in the first tier, and wherein at least one of the first PMOS transistor, the first NMOS transistor and/or the second PMOS transistor are in the second tier, each of the metal lines has a consistent length, and the metal lines include the front side interconnect structure, the back side interconnect structure and the interlayer via.

9 . The memory device of claim 8 , wherein the interconnect structure includes first and second metal layers and a via electrically connecting the first and second metal layers, and wherein the metal lines include the first metal layer, the second metal layer, and the via.

10 . A method, comprising:

providing a substrate having a front side and a back side opposite the front side;

forming active devices of a word line driver circuit configured to output a word line enable signal to a word line of a memory array in or on the substrate, the word line driver circuit including an inverter circuit and an enable transistor, wherein the active devices of the inverter circuit include a first PMOS transistor and a first NMOS transistor, wherein the enable transistor includes a PMOS transistor, and wherein the enable transistor is a FinFET having fewer than 10 fingers;

forming a metal line electrically connecting the inverter circuit, the enable transistor and the word line, wherein forming the metal line includes:

forming an interlayer via extending through the substrate;

forming a front side interconnect structure on or over the front side of the substrate; and

forming a back side interconnect structure on or over the back side of the substrate, such that the metal line electrically connecting the inverter circuit, the enable transistor and the word line includes the front side interconnect structure, the back side interconnect structure and the interlayer via.

11 . The method of claim 10 , wherein forming the front side interconnect structure includes forming first and second metal layers and a via electrically connecting the first and second metal layers, wherein the metal line includes the first and second metal layers and the via.

12 . The method of claim 10 , wherein providing the substrate includes providing a substrate having first and second tiers, wherein at least one of the first PMOS transistor, the first NMOS transistor and/or the second PMOS transistor are in the first tier, and wherein at least one of the first PMOS transistor, the first NMOS transistor and/or the second PMOS transistor are in the second tier.

13 . The memory device of claim 8 , wherein the enable transistor is a FinFET.

14 . The memory device of claim 13 , wherein the FinFET includes fewer than 10 gate fingers.

15 . The memory device of claim 13 , wherein the FinFET includes 7 gate fingers.

16 . The memory device of claim 8 , wherein the metal lines each have a resistance greater than 200 ohms.

17 . The memory device of claim 8 , wherein the metal lines each have a resistance of 200 to 400 ohms.

18 . The method of claim 8 , wherein the metal line has a resistance greater than 200 ohms.

19 . The method of claim 8 , wherein the metal line has a resistance of 200 to 400 ohms.

20 . The method of claim 8 , wherein the memory array includes SRAM cells.