Drain-side wordline voltage boosting to reduce lateral electron field during a programming operation
A request to execute a programming operation to program a set of memory cells associated with a target wordline of a memory device is identified. At a first time during application of a programming voltage to the target wordline, causing a first adjusted pass through voltage to be applied to a first portion of a first set of drain-side wordlines of the memory device. At a second time during application of the programming voltage to the target wordline, causing a second pass through voltage to be applied to a second portion of the first set of drain-side wordlines and to one or more source-side wordlines of the memory device, where the first adjusted pass through voltage is greater than the second pass through voltage.
1 . A memory device comprising:
a memory array; and
control logic, operatively coupled with the memory array, to perform operations comprising:
identifying a request to execute a programming operation to program a set of memory cells associated with a target wordline of the memory array;
causing, prior to application of a programming pulse of the programming operation to the target wordline, a first adjusted pass through voltage to be applied to a first portion of a first set of drain-side wordlines of the memory device, wherein the first adjusted pass through voltage is a first default pass through voltage increased by a first delta voltage level; and
causing, prior to the application of the programming pulse of the programming operation to the target wordline, a second pass through voltage to be applied to a second portion of the first set of drain-side wordlines and to one or more source-side wordlines of the memory device, wherein the first adjusted pass through voltage is greater than the second pass through voltage; and
causing, during application of a target programming voltage level to the target wordline, a ramping down of the first adjusted pass through voltage applied to the first portion of the first set of drain-side wordlines to the first default pass through voltage.
2 . The memory device of claim 1 , wherein the second pass through voltage is a second default pass through voltage level reduced by a second delta voltage level.
3 . The memory device of claim 2 , wherein the first delta voltage level is greater than the second delta voltage level.
4 . The memory device of claim 1 , wherein the first adjusted pass through voltage is applied to the first portion of the first set of drain-side wordlines during application of the second pass through voltage to the target wordline.
5 . The memory device of claim 1 , wherein the first adjusted pass through voltage is ramped down to the first default pass through voltage level after a step-down time period initiated at a start of a pulse time of the programming pulse.
6 . The memory device of claim 1 , the operations further comprising ramping up the second pass through voltage to a second default pass through voltage level in response to the application of the programming pulse of the programming operation to the target wordline.
7 . A method comprising:
identifying, by a processing device, a request to execute a programming operation to program a set of memory cells associated with a target wordline of a memory device;
causing, prior to application of a programming pulse of the programming operation to the target wordline at a first time during application of a programming voltage to the target wordline, a first adjusted pass through voltage to be applied to a first portion of a first set of drain-side wordlines of the memory device, wherein the first adjusted pass through voltage is a first default pass through voltage increased by a first delta voltage level;
causing, prior to the application of the programming pulse of the programming operation to the target wordline at a second time during application of the programming voltage to the target wordline, a second pass through voltage to be applied to a second portion of the first set of drain-side wordlines and to one or more source-side wordlines of the memory device, wherein the first adjusted pass through voltage is greater than the second pass through voltage; and
causing, during application of a target programming voltage level to the target wordline, a ramping down of the first adjusted pass through voltage applied to the first portion of the first set of drain-side wordlines to the first default pass through voltage.
8 . The method of claim 7 , wherein the second pass through voltage is a second default pass through voltage level reduced by a second delta voltage level.
9 . The method of claim 8 , wherein the first delta voltage level is greater than the second delta voltage level.
10 . The method of claim 7 , wherein the first adjusted pass through voltage is applied to the first portion of the first set of drain-side wordlines during application of the second pass through voltage to the target wordline.
11 . The method of claim 7 , wherein the first adjusted pass through voltage is ramped down to the first default pass through voltage level after a step-down time period initiated at a start of a pulse time of the programming pulse.
12 . The method of claim 7 , further comprising ramping up the second pass through voltage to a second default pass through voltage level in response to the application of the programming pulse of the programming operation to the target wordline.
13 . A non-transitory computer readable medium comprising instructions, which when executed by a processing device, cause the processing device to perform operations comprising:
identifying a request to execute a programming operation to program a set of memory cells associated with a target wordline of a memory device;
causing, prior to application of a programming pulse of the programming operation to the target wordline at a first time during application of a programming voltage to the target wordline, a first adjusted pass through voltage to be applied to a first portion of a first set of drain-side wordlines of the memory device, wherein the first adjusted pass through voltage is a first default pass through voltage increased by a first delta voltage level;
causing, prior to the application of the programming pulse of the programming operation to the target wordline at a second time during application of the programming voltage to the target wordline, a second pass through voltage to be applied to a second portion of the first set of drain-side wordlines and to one or more source-side wordlines of the memory device, wherein the first adjusted pass through voltage is greater than the second pass through voltage; and
causing, during application of a target programming voltage level to the target wordline, a ramping down of the first adjusted pass through voltage applied to the first portion of the first set of drain-side wordlines to the first default pass through voltage.
14 . The non-transitory computer readable medium of claim 13 , wherein the second pass through voltage is a second default pass through voltage level reduced by a second delta voltage level.
15 . The non-transitory computer readable medium of claim 14 , wherein the first delta voltage level is greater than the second delta voltage level.
16 . The non-transitory computer readable medium of claim 13 , wherein the first adjusted pass through voltage is applied to the first portion of the first set of drain-side wordlines during application of the second pass through voltage to the target wordline.
17 . The non-transitory computer readable medium of claim 13 , the operations further comprising:
the first adjusted pass through voltage is ramped down to the first default pass through voltage level after a step-down time period initiated at a start of a pulse time of the programming pulse; and
ramping up the second pass through voltage to a second default pass through voltage level in response to the application of the programming pulse of the programming operation to the target wordline.