IP Library › Granted Patent US 12676191
Granted Patent B2
US 12676191 · App. 18/748,679 · Granted Jul 7, 2026

Seeding bias control for sub-block groups in a memory device

Inventors: Taehyun Kim (San Jose, CA); Brian Kwon (San Jose, CA); Dong Kyo Shim (Milpitas, CA); Kwang Ho Kim (Pleasanton, CA); Erwin E. Yu (San Jose, CA); Fulvio Rori (Boise, ID)
Assignee: Micron Technology, Inc.
G11C16/102G11C11/5628G11C16/0483G11C16/08G11C16/10G11C16/32G11C16/3404G11C16/3427
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Quick Facts
Patent No.
US 12676191
App. No.
18/748,679
Granted
Jul 7, 2026
Kind
B2
Abstract

Control logic in a memory device initiates a program operation to program one or more memory cells of a first sub-block of a memory array, the program operation including a seeding phase. During the seeding phase, a first wordline voltage is caused to be applied to a first wordline segment associated with a first portion of the memory array. During the seeding phase, a second wordline voltage is caused to be applied to a second wordline segment associated with a second portion of the memory array, where the first wordline voltage and the second wordline voltage cause a seeding bias voltage to be applied to the first sub-block group and inhibit application of the seeding bias voltage to the second sub-block group.

Claims (33)

1 . A memory device comprising:

a memory array comprising:

a first sub-block group comprising a first sub-block and a second sub-block; and

a second sub-block group comprising a third sub-block and a fourth sub-block; and

control logic, operatively coupled with the memory array, to perform operations comprising:

initiating a program operation to program one or more memory cells of the first sub-block of the memory array, the program operation comprising a seeding phase;

causing, during the seeding phase, a first wordline voltage to be applied to a first wordline segment associated with a first portion of the memory array; and

causing, during the seeding phase, a second wordline voltage to be applied to a second wordline segment associated with a second portion of the memory array, wherein the first wordline voltage and the second wordline voltage cause a seeding bias voltage to be applied to the first sub-block group and inhibit application of the seeding bias voltage to the second sub-block group.

2 . The memory device of claim 1 , wherein one or more of the first wordline voltage or the second wordline voltage satisfies a first condition associated with the second sub-block group.

3 . The memory device of claim 2 , wherein the first condition is satisfied when one or more of the first wordline voltage is less than a first threshold voltage associated with a first memory cell of the third sub-block or the second wordline voltage is less than a second threshold voltage associated with a second memory cell of the fourth sub-block.

4 . The memory device of claim 3 , wherein the first wordline voltage and the second wordline voltage satisfy a second condition associated with the first sub-block group.

5 . The memory device of claim 4 , wherein the second condition is satisfied when the first wordline voltage is greater than a third threshold voltage associated with a third memory cell of the first sub-block and the second wordline voltage is greater than a fourth threshold voltage associated with a fourth memory cell of the second sub-block.

6 . The memory device of claim 1 , wherein a first source bias voltage level is applied during a first subset of programming loops of the programming operation, and wherein a second source bias voltage level that is greater than the first source bias voltage level is applied during a second subset of programming loops of the programming operation.

7 . The memory device of claim 1 , wherein a first source bias voltage level is applied in response to a voltage programming level exceeding a first voltage level, and wherein a second source bias voltage level that is greater than the first source bias voltage level is applied in response to the voltage programming level exceeding a second voltage level.

8 . A method comprising:

initiating a program operation to program one or more memory cells of a first sub-block of a memory device comprising a first sub-block group comprising a first sub-block and a second sub-block and a second sub-block group comprising a third sub-block and a fourth sub-block;

causing, during a seeding phase of the program operation, a first wordline voltage to be applied to a first wordline segment associated with a first portion of a memory array; and

causing, during the seeding phase, a second wordline voltage to be applied to a second wordline segment associated with a second portion of the memory array, wherein the first wordline voltage and the second wordline voltage cause a seeding bias voltage to be applied to the first sub-block group and inhibit application of the seeding bias voltage to the second sub-block group.

9 . The method of claim 8 , wherein one or more of the first wordline voltage or the second wordline voltage satisfies a first condition associated with the second sub-block group.

10 . The method of claim 9 , wherein the first condition is satisfied when one or more of the first wordline voltage is less than a first threshold voltage associated with a first memory cell of the third sub-block or the second wordline voltage is less than a second threshold voltage associated with a second memory cell of the fourth sub-block.

11 . The method of claim 10 , wherein the first wordline voltage and the second wordline voltage satisfy a second condition associated with the first sub-block group.

12 . The method of claim 11 , wherein the second condition is satisfied when the first wordline voltage is greater than a third threshold voltage associated with a third memory cell of the first sub-block and the second wordline voltage is greater than a fourth threshold voltage associated with a fourth memory cell of the second sub-block.

13 . The method of claim 8 , wherein a first source bias voltage level is applied during a first subset of programming loops of the programming operation, and wherein a second source bias voltage level that is greater than the first source bias voltage level is applied during a second subset of programming loops of the programming operation.

14 . The method of claim 8 , wherein a first source bias voltage level is applied in response to a voltage programming level exceeding a first voltage level, and wherein a second source bias voltage level that is greater than the first source bias voltage level is applied in response to the voltage programming level exceeding a second voltage level.

15 . A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:

initiating a program operation to program one or more memory cells of a first sub-block of a memory device comprising a first sub-block group comprising a first sub-block and a second sub-block and a second sub-block group comprising a third sub-block and a fourth sub-block;

causing, during a seeding phase of the program operation, a first wordline voltage to be applied to a first wordline segment associated with a first portion of a memory array; and

causing, during the seeding phase, a second wordline voltage to be applied to a second wordline segment associated with a second portion of the memory array, wherein the first wordline voltage and the second wordline voltage cause a seeding bias voltage to be applied to the first sub-block group and inhibit application of the seeding bias voltage to the second sub-block group.

16 . The non-transitory computer-readable storage medium of claim 15 , wherein one or more of the first wordline voltage or the second wordline voltage satisfies a first condition associated with the second sub-block group, and wherein the first condition is satisfied when one or more of the first wordline voltage is less than a first threshold voltage associated with a first memory cell of the third sub-block or the second wordline voltage is less than a second threshold voltage associated with a second memory cell of the fourth sub-block.

17 . The non-transitory computer-readable storage medium of claim 15 , wherein the first wordline voltage and the second wordline voltage satisfy a second condition associated with the first sub-block group.

18 . The non-transitory computer-readable storage medium of claim 17 , wherein the second condition is satisfied when the first wordline voltage is greater than a third threshold voltage associated with a third memory cell of the first sub-block and the second wordline voltage is greater than a fourth threshold voltage associated with a fourth memory cell of the second sub-block.

19 . The non-transitory computer-readable storage medium of claim 15 , wherein a first source bias voltage level is applied during a first subset of programming loops of the programming operation, and wherein a second source bias voltage level that is greater than the first source bias voltage level is applied during a second subset of programming loops of the programming operation.

20 . The non-transitory computer-readable storage medium of claim 15 , wherein a first source bias voltage level is applied in response to a voltage programming level exceeding a first voltage level, and wherein a second source bias voltage level that is greater than the first source bias voltage level is applied in response to the voltage programming level exceeding a second voltage level.