IP Library › Granted Patent US 12676193
Granted Patent B2
US 12676193 · App. 18/824,083 · Granted Jul 7, 2026

Non-volatile memory with adjustable erase voltage

Inventors: Xuan Tian (Shanghai, CN); Liang Li (Shanghai, CN); Jojo Xing (Shanghai, CN)
Assignee: Sandisk Technologies, Inc.
G11C16/16G11C16/32G11C16/349
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Quick Facts
Patent No.
US 12676193
App. No.
18/824,083
Granted
Jul 7, 2026
Kind
B2
Abstract

An adjustable kick voltage and an adjustable time duration are adjusted/set based on one or more conditions of a non-volatile memory. During an erase process, an erase voltage pulse is applied to a set of non-volatile memory cells of the non-volatile memory including driving an erase pulse voltage magnitude to an elevated voltage that is equal to a base erase voltage plus the adjusted kick voltage for the adjusted time duration and then reducing the erase pulse voltage magnitude to the base erase voltage for the remainder of the erase voltage pulse.

Claims (60)

1 . A non-volatile memory apparatus, comprising:

non-volatile memory comprising non-volatile memory cells; and

a control circuit connected to the non-volatile memory, the control circuit is configured to:

set an adjustable kick voltage based on one or more conditions of the non-volatile memory, and

apply an erase voltage pulse to the non-volatile memory cells including driving an erase pulse voltage magnitude to an elevated voltage that is equal to a base erase voltage plus the adjustable kick voltage for a time duration and then reducing the erase pulse voltage magnitude to the base erase voltage, the time duration is an adjustable time duration, the control circuit is configured to set the adjustable time duration based on the one or more conditions of the non-volatile memory.

2 . The non-volatile memory apparatus of claim 1 , wherein:

the one or more conditions of the non-volatile memory include temperature such that the control circuit is configured to set the adjustable kick voltage based on temperature.

3 . The non-volatile memory apparatus of claim 1 , wherein:

the one or more conditions of the non-volatile memory include temperature; and

the control circuit is configured to set the adjustable kick voltage as a base kick voltage plus an additional voltage based on temperature.

4 . The non-volatile memory apparatus of claim 1 , wherein:

the one or more conditions of the non-volatile memory include current temperature; and

the control circuit is configured to set the adjustable kick voltage as a base kick voltage plus an additional voltage based on a difference between current temperature and a baseline temperature.

5 . The non-volatile memory apparatus of claim 1 , wherein:

the one or more conditions of the non-volatile memory include current temperature; and

the control circuit is configured to set the adjustable kick voltage as a base kick voltage plus a multiple of an additional voltage based on a difference between current temperature and a baseline temperature.

6 . The non-volatile memory apparatus of claim 1 , wherein:

the one or more conditions of the non-volatile memory include temperature such that the control circuit is configured to set the adjustable time duration based on temperature.

7 . The non-volatile memory apparatus of claim 1 , wherein:

the one or more conditions of the non-volatile memory include temperature; and

the control circuit is configured to set the adjustable time duration as a base time duration plus an additional duration based on temperature.

8 . The non-volatile memory apparatus of claim 1 , wherein:

the one or more conditions of the non-volatile memory include current temperature; and

the control circuit is configured to set the adjustable time duration as a base time duration plus a multiple of an additional time duration based on a difference between current temperature and a baseline temperature.

9 . The non-volatile memory apparatus of claim 1 , wherein:

the one or more conditions of the non-volatile memory include temperature;

the control circuit is configured to set the adjustable time duration as a base time duration plus an additional duration based on temperature; and

the control circuit is configured to set the adjustable kick voltage as a base kick voltage plus an additional voltage based on temperature.

10 . A non-volatile memory apparatus, comprising:

non-volatile memory comprising non-volatile memory cells, the non-volatile memory further comprises a plurality of Gate Induced Drain Leakage (“GIDL”) generation transistors connected to the non-volatile memory cells; and

a control circuit connected to the non-volatile memory, the control circuit is configured to:

set an adjustable kick voltage based on one or more conditions of the non-volatile memory, and

apply an erase voltage pulse to the non-volatile memory cells including driving an erase pulse voltage magnitude to an elevated voltage that is equal to a base erase voltage plus the adjustable kick voltage for a time duration and then reducing the erase pulse voltage magnitude to the base erase voltage;

the control circuit is configured to test whether more than a predetermined number of the GIDL generation transistors have threshold voltages greater than a test magnitude; and

the control circuit is configured to set the kick voltage based on one or more conditions of the non-volatile memory by adjusting the kick voltage in response to determining that more than the predetermined number of the GIDL generation transistors have threshold voltages greater than the test magnitude.

11 . The non-volatile memory apparatus of claim 10 , wherein:

the control circuit is configured to adjust the kick voltage based on number of the GIDL generation transistors having threshold voltages greater than the test magnitude.

12 . The non-volatile memory apparatus of claim 10 , wherein:

the control circuit is configured to perform the test in response to a predetermined number of program/erase cycle performed.

13 . The non-volatile memory apparatus of claim 10 , wherein:

the control circuit is configured to adjust the time duration in response to determining that more than the predetermined number of the GIDL generation transistors have threshold voltages greater than the test magnitude.

14 . The non-volatile memory apparatus of claim 1 , wherein:

the non-volatile memory further comprises a plurality of Gate Induced Drain Leakage (“GIDL”) generation transistors connected to the non-volatile memory cells;

the control circuit is configured to test whether more than a predetermined number of the GIDL generation transistors have threshold voltages greater than a test magnitude;

the control circuit is configured to set the kick voltage based on one or more conditions of the non-volatile memory by adjusting the kick voltage in response to determining that more than the predetermined number of the GIDL generation transistors have threshold voltages greater than the test magnitude and based on temperature;

the control circuit is configured to set the time duration by adjusting the time duration in response to determining that more than the predetermined number of the GIDL generation transistors have threshold voltages greater than the test magnitude and based on temperature.

15 . A method, comprising:

applying an erase voltage pulse to a set of non-volatile memory cells including driving an erase pulse voltage magnitude to an elevated voltage that is equal to a base erase voltage plus an adjustable kick voltage for an adjustable time duration and then reducing the erase pulse voltage magnitude to the base erase voltage;

determining a condition of a non-volatile memory that comprises the non-volatile memory cells;

adjusting the adjustable kick voltage based on the determined condition; and

adjusting the adjustable time duration based on the determined condition.

16 . The method of claim 15 , wherein:

the condition is temperature.

17 . The method of claim 15 , wherein:

the determining the condition comprises determining that a population of Gate Induced Drain Leakage (“GIDL”) generation transistors connected to the non-volatile memory cells has more than a predetermined number of transistors with threshold voltages greater than a test magnitude;

the adjusting the adjustable kick voltage and the adjusting the adjustable time duration are performed in response to the determining that the population of GIDL generation transistors has more than the predetermined number of transistors with threshold voltages greater than the test magnitude; and

the adjusting the adjustable kick voltage and the adjusting the adjustable time duration are performed prior to the applying the erase voltage pulse.

18 . A non-volatile memory apparatus, comprising:

non-volatile memory comprising non-volatile memory cells; and

means for applying an erase voltage pulse to the non-volatile memory cells including driving an erase pulse voltage magnitude to an elevated voltage that is equal to a base erase voltage plus a kick voltage that is adjustable based on a condition of the non-volatile memory for a time duration that is adjustable based on the condition of the non-volatile memory and then reducing the erase pulse voltage magnitude to the base erase voltage.