Memory system and operation method of memory system
A memory system includes: an address scrambler suitable for scrambling an address based on a scrambling rule to generate a scrambled address; a memory core including a plurality of memory cells and suitable for storing data in memory cells designated by the scrambled address; and a scramble control circuit suitable for changing the scrambling rule in response to satisfaction of an attack condition.
1 . An operating method of a controller of a memory system, the operating method comprising:
detecting a row hammer attack pattern for one row of memory cells within a memory device;
determining an error equal to or greater than a threshold value which occurs in neighboring rows of the one row;
changing a scrambling pattern upon a determining result; and
controlling the memory device to access the memory core according to an address scrambled by the changed scrambling pattern.
2 . The operating method of claim 1 , further comprising controlling the memory device to:
back up data stored in the memory core before the changing; and
restore the backed-up data back into the memory core after the changing.
3 . The operating method of claim 1 ,
wherein the detecting, the determining, and the changing are performed by the controller within the memory system, and
wherein the controlling is performed by the memory device within the memory system.
4 . The operating method of claim 1 ,
wherein the changing the scrambling pattern is performed by an address scrambler.
5 . The operating method of claim 4 ,
wherein the address scrambler is located in the controller within the memory system.
6 . The operating method of claim 4 ,
wherein the address scrambler is located in the memory core within the memory system.