Devices and processes for arc suppression in electrical panels
It addresses to a process and device capable of mitigating electric arc faults in electrical panels as quickly as a few milliseconds. The technology uses power thyristors that, after detecting the arc, make the electrical connection of the panel's input bus to ground potential in a controlled manner, diverting the arc currents to this preferred path and forcing their extinction. The proposed suppressor device has improved features, as it includes a “snubber” that forms with the current limiting impedance with inductive reactive component a resonant circuit of Resistance, Inductance (L) and Capacitance (RLC). The “snubber” is capable of mitigating adverse consequences of the RLC circuit voltage transient due to the thyristor shutdown, protecting the same against voltage rises and spurious triggers and limiting the voltage on the panel bus to values below those capable of sustaining the arc fault. The technology relates to equipment for industrial and commercial electrical systems, specifically load distribution centers (LDC) or motor control centers (MCC), which can be configured as a compartment within a LDC or MCC.
1 . A process for suppressing electric arcs, the process comprising:
a) in a three-phase circuit in which it is desired to suppress electric arcs, identifying a voltage threshold (V limiar ) from which it is possible for a phase-to-ground arc fault to occur on a bus using a Kizilcay model;
b) calculating an impedance Zx of a suppressor using expression (I) from known values Rc and Zs, where RC is a resistance of a thyristor in conduction mode, and Zs is equivalent impedance of an electrical system;
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Z
x
+
R
c
Z
s
+
Z
x
+
R
c
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·
V
s
<
V
limiar
(
I
)
c) calculating a voltage rise on the bus due to circulation of a current (Im) demanded by at least one load connected in parallel with the suppressor and fed by the electrical system by applying a product [(Zx//Zs)×Im], if the calculated voltage rise provides a voltage on the bus greater than V limiar calculated in step (a), decreasing Zx until the voltage on the bus is lower than V limiar ;
d) defining a Xx/Rx ratio for the impedance (Zx) calculated in step (b);
e) calculating an inductive reactance (Xx) and a resistance (Rx) associated with the impedance Zx based on the Xx/Rx ratio defined in step (d);
f) calculating a resistance (Rs) and a capacitance (Cs) of a snubber ( 4 ) by applying a classical solution to a second-order linear differential equation obtained from a RLC (Resistance, Inductance and Capacitance) series circuit and a response of the RLC series circuit to a voltage step (E), so that, after solving in a time domain by means of an inverse Laplace transform, a voltage (V T(t) ) on the snubber is obtained, which is a same voltage on the thyristor and which is transmitted by an inductance (Lx) to the bus that is subject to an overvoltage that can be generated by an RLC circuit transient that occurs during a shutdown of the thyristor, wherein a solution is given by choosing between expressions (II), (III), (IV) resulting from the inverse Lapace transform based on a defined damping factor (ξ), and for circuits with underdamped oscillations 0≤ξ≤1, expression (II) is used:
V
T
(
t
)
=
E
-
E
·
(
cos
(
ω
p
·
t
)
+
(
2
·
(
1
-
M
)
-
1
)
·
ξω
0
ω
p
·
sin
(
ω
p
·
t
)
)
·
e
-
ξ
·
ω
0
·
t
(
II
)
in expression (II), the relation between an undamped natural frequency (ω o ) and a damped frequency (ω p ) is:
ω
p
=
ω
0
·
1
-
ξ
2
for circuits with damped oscillation ξ=1, expression (III) is used:
V
T
(
t
)
=
E
-
E
·
(
1
+
(
2
·
(
1
-
M
)
-
1
)
·
ω
0
·
t
)
·
e
-
ω
0
·
t
(
III
)
for circuits with overdamped oscillation ξ>1, expression (IV) is used:
V
T
(
t
)
=
E
-
E
·
(
cos
h
(
ω
p
·
t
)
+
(
2
·
(
1
-
M
)
-
1
)
·
ξω
0
ω
p
·
sin
h
(
ω
p
·
t
)
)
·
e
-
ξ
·
ω
0
·
t
(
IV
)
in expression (IV), the relation between the undamped natural frequency (ω o ) and the damped frequency (ω p ) is:
ω
p
=
ω
0
·
ξ
2
-
1
the values of M and ξ can be obtained by using expressions (V) and (VI) below:
M
=
R
S
R
S
+
R
x
(
V
)
ξ
=
(
R
S
+
R
x
)
(
Ω
)
2
·
C
S
(
F
)
L
x
(
H
)
(
VI
)
a chosen expression of V T(t) (II, III or IV) must be solved to obtain a value of Cs as large and a value of Rs as small as possible so that a contribution of V T(t) does not increase the bus voltage for values greater than the voltage threshold (V limiar ) calculated in step (a) and, at the same time, satisfy threshold conditions for current variation in a ligament (di/dt turn-on ) supportable by the thyristor, wherein the snubber assumes a specific complementary function in the suppressor of limiting voltage rise due to transients that can increase the voltage on the bus and trigger or sustain an arc fault, where the snubber forms a resonant circuit with the impedance (Zx);
g) defining a peak current threshold (Ipk) that can circulate in a capacitor of the snubber by applying a ratio Vs/Rs, wherein Rs is the resistance of the snubber calculated in step (f) and wherein Vs is the peak voltage of the snubber;
h) choosing the capacitor of the snubber based on the requirements calculated in steps (f) and (g);
i) Applying to the suppressor, in its constituent electrical and electronic elements, the values calculated in steps “a” to “g”: Rx, Lx, Cs and Rs;
j) commanding, using an electric arc sensor activation of the suppressor configured in step (i) when a formation of an electric arc is detected, wherein the activation is intermediated by a control unit with independent electrical power supply, which includes trigger circuits of the thyristor and auxiliary circuits for measuring voltages and currents of the suppressor and signal conditioning that operate the suppressor as a voltage clamp capable of maintaining the voltage on the bus below the V limiar value until the electric arc formed is completely extinguished.
2 . The process for suppressing electric arcs according to claim 1 , wherein the process is adapted to the context of an arc fault of a three-phase short circuit to ground, initially considering the operation in steady state which, according to Fortescue's theorem, has only positive sequence current, which allows the three-phase system to be reduced to a single-phase equivalent to which the formulations of claim 1 can be applied by changing variables from a phase domain to symmetrical components.
3 . The process for suppressing electric arcs according to claim 1 , wherein, according to step (d), the relation Xx/Rx for the impedance Zx of the suppressor is equal to 5.
4 . The process for suppressing electric arcs according to claim 1 , further comprising, according to step (j), commanding reconnection of a input circuit breaker after extinction of the electric arc, thereby reestablishing the normal operation of the circuit.
5 . A device for suppressing electric arcs, configured to perform the process of claim 1 , the device comprising the suppressor containing a pair of thyristors in antiparallel connection, the gate terminals of the pair of thyristors connected to the control unit, wherein the suppressor is connected to the bus and has the current limiting impedance (Zx) consisting of the inductance (Lx) and the resistance (Rx) and is connected to the pair of thyristors in antiparallel connection connected to the snubber comprising a capacitor and a resistor, wherein the suppressor is configured to operate in conjunction with an independent and uninterruptible power supply, the control unit that includes the trigger circuits of the thyristors and the auxiliary circuits for measuring voltages and currents of the suppressor and signal conditioning, also includes the electric arc sensor, and an arc sensor relay that commands the activation of the suppressor, the independent power supply that supplies energy to the control unit, for the electric arc sensor and the arc sensor relay, where the snubber assumes a specific complementary function in the suppressor of limiting voltage rises due to transients which can increase the voltage on the bus and trigger or sustain an arc fault, the snubber forms a resonant circuit with the impedance (Zx) that mitigates adverse consequences of a voltage transient, protecting the thyristors against voltage rises and spurious triggers and limiting the voltage on the bus below V limiar .
6 . The device for suppressing electric arcs according to claim 5 , wherein the pair of thyristors are press pack type thyristors, which have their short circuit failure mode.
7 . The device for suppressing electric arcs according to claim 5 , wherein the capacitor is in polypropylene or film.
8 . The device for suppressing electric arcs according to claim 5 , wherein the resistor is non-inductive and is manufactured from carbon film.