Constant power startup for power converter
Circuits and methods for providing a constant, limited power to a transistor of a power converter during a startup period while achieving high efficiency and high performance. In a first embodiment, a driver circuit includes a variable reference current circuit configured to provide a first current inversely proportional to a voltage across the transistor, and a coupled power limiting circuit that enables a second current through the transistor that is proportional to the first current. In a second embodiment, a driver circuit includes a variable reference current circuit configured to provide a first current that increases over a time period of operation as a function of a voltage at a node of the power converter, and a coupled power limiting circuit that enables a second current through the transistor that is proportional to the first current and inversely proportional to a voltage across the transistor.
1 . A driver circuit configured to maintain approximately constant power through a transistor of a power converter during a time period of operation of the power converter, the driver circuit comprising:
a variable reference current circuit configured to provide a first current that is inversely proportional to a voltage across the transistor; and
a power limiting circuit coupled to the variable reference current circuit and to the transistor, wherein the power limiting circuit is configured to provide a control voltage to a control input of the transistor based on the first current to cause the transistor to pass a second current proportional to the first current in which the second current changes the voltage across the transistor such that power through the transistor is maintained approximately constant.
2 . The driver circuit of claim 1 , wherein the transistor of the power converter is a FET.
3 . The driver circuit of claim 1 , wherein the transistor of the power converter is a FET, and the voltage across the FET is a drain-to-source voltage V DS .
4 . The driver circuit of claim 1 , wherein the power limiting circuit is configured to provide the control voltage to cause the transistor to pass the second current through the transistor during a startup period of the power converter.
5 . The driver circuit of claim 1 , wherein the power limiting circuit is configured to provide the control voltage to cause the transistor to pass the second current through the transistor during a soft-startup period of the power converter commencing from an OFF state of the power converter.
6 . The driver circuit of claim 1 , wherein the first current is inversely proportional to V IN −(n×V OUT ), where V IN is an input voltage to the power converter, V OUT is an output voltage of the power converter, and n is a conversion ratio of the power converter.
7 . The driver circuit of claim 1 , wherein the first current is proportional to one of V OUT or V FCx , where V OUT is an output voltage of the power converter and V FCx is a voltage across a fly capacitor of the power converter.
8 . The driver circuit of claim 1 , wherein the second current is inversely proportional to V IN −(n×V OUT ), where V IN is an input voltage to the power converter, V OUT is an output voltage of the power converter, and n is a conversion ratio of the power converter.
9 . The driver circuit of claim 1 , wherein the second current is proportional to one of V OUT or V FCx , where V OUT is an output voltage of the power converter and V FCx is a voltage across a fly capacitor of the power converter.
10 . The driver circuit of claim 1 , wherein the power limiting circuit includes:
a first FET having a conduction channel coupled between a gate of the transistor and a reference voltage;
a second FET having a conduction channel having a first terminal coupled to a voltage source and a second terminal coupled to a gate of the second FET; and
a third FET having a gate coupled to a gate of the first FET and a conduction channel having a first terminal coupled to the second terminal of the second FET and a second terminal coupled to the gate of the third FET and to the variable reference current circuit.
11 . The driver circuit of claim 1 , wherein to maintain the power of the transistor approximately constant, in response to a decrease in the voltage across the transistor, the variable reference current circuit and the power limiting circuit are cooperatively configured to increase the second current.
12 . A driver circuit configured to maintain approximately constant power through a transistor of a power converter, the driver circuit comprising:
a variable reference current circuit configured to provide a first current based on a voltage at a node of the power converter; and
a power limiting circuit coupled to the variable reference current circuit and to the transistor, wherein the power limiting circuit is configured to provide a control voltage to a control input of the transistor based on the first current to cause the transistor to pass a second current proportional to the first current and inversely proportional to a voltage across the transistor in which the second current changes the voltage across the transistor such that power through the transistor is maintained approximately constant.
13 . The driver circuit of claim 12 , wherein the transistor of the power converter is a FET.
14 . The driver circuit of claim 12 , wherein the transistor of the power converter is a FET, and the voltage across the FET is a drain-to-source voltage V DS .
15 . The driver circuit of claim 12 , wherein the power limiting circuit is configured to provide the control voltage to cause the transistor to pass the second current through the transistor during a startup period of the power converter.
16 . The driver circuit of claim 12 , wherein the power limiting circuit is configured to provide the control voltage to cause the transistor to pass the second current through the transistor during a soft-startup period of the power converter commencing from an OFF state of the power converter.
17 . The driver circuit of claim 12 , wherein the first current is inversely proportional to V IN −(n×V OUT ), where V IN is an input voltage to the power converter, V OUT is an output voltage of the power converter, and n is a conversion ratio of the power converter.
18 . The driver circuit of claim 12 , wherein the first current is proportional to one of V OUT or V FCx , where V OUT is an output voltage of the power converter and V FCx is a voltage across a fly capacitor of the power converter.
19 . The driver circuit of claim 12 , wherein the second current is inversely proportional to V IN −(n×V OUT ), where V IN is an input voltage to the power converter, V OUT is an output voltage of the power converter, and n is a conversion ratio of the power converter.
20 . The driver circuit of claim 12 , wherein the second current is proportional to one of V OUT or V FCx , where V OUT is an output voltage of the power converter and V FCx is a voltage across a fly capacitor of the power converter.
21 . The driver circuit of claim 12 , wherein the power limiting circuit includes:
a first FET having a conduction channel coupled between a gate of the transistor and a reference voltage;
a second FET having a conduction channel having a first terminal coupled to a voltage source and a second terminal coupled to a gate of the second FET; and
a third FET having a gate coupled to a gate of the first FET and a conduction channel having a first terminal coupled to the second terminal of the second FET and a second terminal coupled to the gate of the third FET and to the variable reference current circuit.
22 . The driver circuit of claim 12 , wherein to maintain the power of the transistor approximately constant, in response to a decrease in the voltage across the transistor, the variable reference current circuit and the power limiting circuit are cooperatively configured to increase the second current.