Crystal oscillators including a two stage amplifier

1 . A crystal oscillator comprising:

a two stage amplifier comprising a transconductance amplifier stage electrically connected to a class AB output amplifier stage with open loop drive level control, the two stage amplifier to provide a negative resistance; and

a crystal electrically connected between an input of the two stage amplifier and an output of the two stage amplifier.

2 . The crystal oscillator of claim 1 , further comprising:

a phase corrector comprising an input electrically connected to the input of the two stage amplifier; and

a comparator comprising a first input electrically connected to the output of the two stage amplifier, a second input electrically connected to an output of the phase corrector, and an output to provide a clock signal based on the first input and the second input.

3 . The crystal oscillator of claim 2 , wherein the phase corrector comprises a resistor-capacitor (RC) circuit.

4 . The crystal oscillator of claim 1 , further comprising:

a resistor electrically connected between the output of the two stage amplifier and the input of the two stage amplifier.

5 . The crystal oscillator of claim 1 , wherein the class AB output amplifier stage comprises a source-follower amplifier stage.

6 . The crystal oscillator of claim 1 , wherein the class AB output amplifier stage comprises a voltage gain of 1.

7 . The crystal oscillator of claim 1 , wherein the class AB output amplifier stage comprises a push-pull class AB output amplifier stage.

8 . The crystal oscillator of claim 1 , wherein the open loop drive level control comprises current limiting at the class AB output amplifier stage via current clamps.

9 . A device comprising:

a crystal oscillator to generate a clock signal, the crystal oscillator comprising:

a two stage amplifier comprising a transconductance amplifier stage electrically connected to a class AB output amplifier stage with open loop drive level control, the two stage amplifier to provide a negative resistance; and

a crystal electrically connected between an input of the two stage amplifier and an output of the two stage amplifier; and

a circuit electrically connected to the crystal oscillator and configured to operate based on the clock signal.

10 . The device of claim 9 , wherein the crystal oscillator further comprises:

a phase corrector comprising an input electrically connected to the input of the two stage amplifier; and

a comparator comprising a first input electrically connected to the output of the two stage amplifier, a second input electrically connected to an output of the phase corrector, and an output to provide the clock signal based on the first input and the second input.

11 . The device of claim 9 , wherein the class AB output amplifier stage comprises a push-pull class AB output amplifier stage.

12 . The device of claim 9 , wherein the class AB output amplifier stage comprises a voltage gain less than or equal to 1.

13 . The device of claim 9 , wherein the class AB output amplifier stage comprises a source-follower amplifier stage.

14 . The device of claim 9 , wherein the open loop drive level control comprises current limiting at the class AB output amplifier stage.

15 . The device of claim 9 , wherein the circuit comprises a microcontroller.

16 . The device of claim 9 , wherein the device comprises a wireless device.

17 . The device of claim 9 , wherein the device comprises a comprises a watch.

18 . A method for generating a clock signal, the method comprising:

amplifying an input signal on a first terminal of a crystal via a two stage amplifier to provide an output signal on a second terminal of the crystal, the two stage amplifier comprising a transconductance amplifier stage and a class AB output amplifier stage with open loop drive level control, the two stage amplifier to provide a negative resistance; and

generating a clock signal based on the output signal.

19 . The method of claim 18 , wherein generating the clock signal based on the output signal comprises:

phase shifting the input signal to generate a phase shifted input signal; and

comparing the output signal to the phase shifted input signal to generate the clock signal.

20 . The method of claim 19 , wherein phase shifting the input signal comprises filtering the input signal to generate the phase shifted input signal.