IP Library Granted Patent US 12676600
Granted Patent B2
US 12676600 · App. 18/097,472 · Granted Jul 7, 2026

Two-stage solid-state match

Inventor: Gideon Van Zyl (Fort Collins, CO)
Assignee: Advanced Energy Industries, Inc.
H03H11/28H01J37/32183H01J2237/24564
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Quick Facts
Patent No.
US 12676600
App. No.
18/097,472
Granted
Jul 7, 2026
Kind
B2
Abstract

This disclosure describes systems, methods, and apparatuses for a two-stage solid state match having a load side and a source side; a first coarse stage and a second precision stage, wherein the first coarse stage is coupled between the second precision stage and the load side, and wherein the second precision stage is coupled between the source side and an input of the first coarse stage; the coarse first stage comprising at least one switched variable reactance element, wherein the coarse first stage is configured to map a load impedance connected to the load side to a first number of intermediate impedances at the input of the first coarse stage; and wherein the second precision stage is configured to map at least one of the intermediate impedances to a second number of input impedances at the source side.

Claims (31)

1 . An apparatus comprising:

a load side and a source side;

a first coarse stage and a second precision stage, wherein the first coarse stage is coupled between the second precision stage and the load side, and wherein the second precision stage is coupled between the source side and an input of the first coarse stage;

the first coarse stage comprising a first switched variable reactance element, wherein the first coarse stage is configured to map a load impedance connected to the load side to a first number of intermediate impedances at the input of the first coarse stage; and

the second precision stage comprising a second switched variable reactance element is configured to map at least one of the intermediate impedances to a second number of input impedances at the source side.

2 . The apparatus of claim 1 , wherein the second switched variable reactance element comprises at least two reactances, comprising an inductive reactance and a capacitive reactance, and wherein the at least two reactances are configured to be switched in and out of the second switched variable reactance element.

3 . The apparatus of claim 1 , wherein the second number of input impedances is greater than the first number of intermediate impedances.

4 . The apparatus of claim 1 , wherein the first number of intermediate impedances is less than or equal to 400.

5 . The apparatus of claim 1 , wherein the second number of input impedances is at least 100,000.

6 . The apparatus of claim 1 , wherein the first coarse stage comprises:

a coarse series element and a coarse shunt element, and wherein the coarse series element or the coarse shunt element comprises the first switched variable reactance element;

wherein the coarse series element is coupled to the load side; and

wherein the coarse shunt element is coupled between the coarse series element and the second precision stage.

7 . The apparatus of claim 6 , wherein the coarse shunt element comprises at least a first switch arranged in series with an inductive reactance and a second switch arranged in series with a capacitive reactance.

8 . The apparatus of claim 6 , wherein the coarse series element comprises at least a first switch arranged in parallel with an inductive reactance and a second switch arranged in parallel with a capacitive reactance.

9 . The apparatus of claim 6 , wherein the first coarse stage further comprises a plurality of PIN diodes.

10 . An apparatus comprising:

a load side and a source side;

a first stage comprising at least one reactance element, wherein the first stage is configured to map a load impedance connected to the load side to a first number of intermediate impedances at an input of the first stage; and

a second stage comprising a first switched variable reactance element configured to map at least one of the intermediate impedances to a second number of input impedances at the source side.

11 . The apparatus of claim 10 , wherein the at least one reactance element comprises at least two reactances, comprising an inductive reactance and a capacitive reactance, and wherein the at least two reactances are configured to be switched in and out of the at least one reactance element.

12 . The apparatus of claim 10 , wherein the second number of input impedances is greater than the first number of intermediate impedances.

13 . The apparatus of claim 10 , wherein the first number of intermediate impedances is less than or equal to 400.

14 . The apparatus of claim 10 , wherein the second number of input impedances is at least 100,000.

15 . The apparatus of claim 10 , wherein the first stage comprises:

a coarse series element and a coarse shunt element, wherein the coarse series element or the coarse shunt element comprises a second switched variable reactance element;

wherein the coarse series element is coupled to the load side; and

wherein the coarse shunt element is coupled between the coarse series element and the second stage.

16 . The apparatus of claim 15 , wherein the first stage further comprises a plurality of PIN diodes.

17 . The apparatus of claim 15 , wherein the coarse shunt element comprises at least a first switch arranged in series with an inductive reactance and a second switch arranged in series with a capacitive reactance.

18 . The apparatus of claim 15 , wherein the coarse series element comprises at least a first switch arranged in parallel with an inductive reactance and a second switch arranged in parallel with a capacitive reactance.