AC coupling modules for bias ladders
A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its V GS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero V GS type, or a mix of positive-logic and zero V GS type FETs with end-cap FETs of the zero V GS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.
1 . A method of biasing a field-effect transistor (FET) switch stack, the method comprising:
providing a plurality of series-coupled FETs, wherein each FET of the plurality of series-coupled FETs comprises a gate, wherein the plurality of series-coupled FETs comprises one or more series-coupled positive-logic FETs requiring a relative negative V GS to effectively turn OFF but configured to not require a negative voltage source, wherein the one or more series-coupled positive logic FETs are series-coupled on at least one end to an end-cap FET configured to turn OFF when the V GS of the end-cap FET is essentially zero volts;
coupling a first gate bias resistor ladder to the plurality of series-coupled FETs, the first gate bias resistor ladder comprising a plurality of parallel-coupled constant-valued resistors, wherein each constant-valued resistor of the first gate bias resistor ladder is coupled to the gate of one corresponding FET of the plurality of series-coupled FETs; and
coupling a second gate bias resistor ladder to the first gate bias resistor ladder, the second gate bias resistor ladder comprising a plurality of series-coupled variable-valued resistors, wherein each variable-valued resistor of the second gate bias resistor ladder is coupled to one corresponding constant-valued resistor of the first gate bias resistor ladder.
2 . The method of claim 1 , further comprising configuring the second gate bias resistor ladder to be coupled to a bias voltage at a node at a first end of the second gate bias resistor ladder.
3 . The method of claim 1 , further comprising configuring the second gate bias resistor ladder to be coupled to a bias voltage at a node between a first end and a second end of the second gate bias resistor ladder.
4 . The method of claim 1 , further comprising providing a second end-cap FET configured to turn OFF when the V GS of the second end-cap FET is essentially zero volts, wherein the second end-cap FET is series-coupled to a second end of the one or more series-coupled positive-logic FETs.
5 . The method of claim 1 , further comprising:
coupling an AC coupling gate module to at least one of the first gate bias resistor ladder or the second gate bias resistor ladder; and
configuring the AC coupling gate module to be coupled to a radio frequency voltage source.
6 . The method of claim 1 , wherein at least one FET of the plurality of series-coupled FETs is an accumulated charge sink (ACS) FET.
7 . A method of biasing a field-effect transistor (FET) switch stack, the method comprising:
providing a plurality of series-coupled FETs, wherein each FET of the plurality of series-coupled FETs comprises a gate, wherein the plurality of series-coupled FETs comprises one or more series-coupled positive-logic FETs requiring a relative negative V GS to effectively turn OFF but configured to not require a negative voltage source, wherein the one or more series-coupled positive logic FETs are series-coupled on at least one end to an end-cap FET configured to turn OFF when the V GS of the end-cap FET is essentially zero volts;
coupling a first gate bias resistor ladder to the plurality of series-coupled FETs, the first gate bias resistor ladder comprising a plurality of parallel-coupled variable-valued resistors, wherein each variable-valued resistor of the first gate bias resistor ladder is coupled to the gate of one corresponding FET of the plurality of series-coupled FETs; and
coupling a second gate bias resistor ladder to the first gate bias resistor ladder, the second gate bias resistor ladder comprising a plurality of series-coupled constant-valued resistors, wherein each constant-valued resistors of the second gate bias resistor ladder is coupled to one corresponding variable-valued resistor of the first gate bias resistor ladder.
8 . The method of claim 7 , further comprising configuring the second gate bias resistor ladder to be coupled to a bias voltage at a node at a first end of the second gate bias resistor ladder.
9 . The method of claim 7 , further comprising configuring the second gate bias resistor ladder to be coupled to a bias voltage at a node between a first end and a second end of the second gate bias resistor ladder.
10 . The method of claim 7 , further comprising providing a second end-cap FET configured to turn OFF when the V GS of the second end-cap FET is essentially zero volts, wherein the second end-cap FET is series-coupled to a second end of the one or more series-coupled positive-logic FETs.
11 . The method of claim 7 , further comprising:
coupling an AC coupling gate module to at least one of the first gate bias resistor ladder or the second gate bias resistor ladder; and
configuring the AC coupling gate module to be coupled to a radio frequency voltage source.
12 . The method of claim 7 , wherein at least one FET of the plurality of series-coupled FETs is an accumulated charge sink (ACS) FET.
13 . A method of biasing a field-effect transistor (FET) switch stack, the method comprising:
providing a plurality of series-coupled FETs, wherein each FET of the plurality of series-coupled FETs comprises a gate, wherein the plurality of series-coupled FETs comprises one or more series-coupled positive-logic FETs requiring a relative negative V GS to effectively turn OFF but configured to not require a negative voltage source, wherein the one or more series-coupled positive logic FETs are series-coupled on at least one end to an end-cap FET configured to turn OFF when the V GS of the end-cap FET is essentially zero volts;
coupling a first gate bias resistor ladder to the plurality of series-coupled FETs, the first gate bias resistor ladder comprising a plurality of parallel-coupled variable-valued resistors, wherein each variable-valued resistor of the first gate bias resistor ladder is coupled to the gate of one corresponding FET of the plurality of series-coupled FETs; and
coupling a second gate bias resistor ladder to the first gate bias resistor ladder, the second gate bias resistor ladder comprising a plurality of series-coupled variable-valued resistors, wherein each valuable-valued resistor of the second gate bias resistor ladder is coupled to one corresponding variable-valued resistor of the first gate bias resistor ladder.
14 . The method of claim 13 , further comprising configuring the second gate bias resistor ladder to be coupled to a bias voltage at a node at a first end of the second gate bias resistor ladder.
15 . The method of claim 13 , further comprising configuring the second gate bias resistor ladder to be coupled to a bias voltage at a node between a first end and a second end of the second gate bias resistor ladder.
16 . The method of claim 13 , further comprising providing a second end-cap FET of a type that turns OFF when the V GS of the second end-cap FET is essentially zero volts, wherein the second end-cap FET is series-coupled to a second end of the one or more series-coupled positive-logic FETs.
17 . The method of claim 13 , further comprising:
coupling an AC coupling gate module to at least one of the first gate bias resistor ladder and the second gate bias resistor ladder; and
configuring the AC coupling gate module to be coupled to a radio frequency voltage source.