Buffer circuit having enhanced slew rate

1 . A buffer circuit for generating an output voltage based on an input voltage, comprising:

an input stage, a load stage, and an output stage, wherein the input stage is configured to provide first and second differential currents to the load stage or receive third and fourth differential currents from the load stage based on a difference between the input voltage and the output voltage,

wherein the load stage is configured to apply gate voltages to first and second output transistors of the output stage based on the first to fourth differential currents, and

wherein the output stage is configured to regulate the output voltage based on the gate voltages applied to the first and the second output transistors;

a slew rate compensation circuit configured to provide a first slew rate compensation current to the load stage or receive a second slew rate compensation current from the load stage based on the difference between the input voltage and the output voltage;

an offset control signal output stage configured to output an offset control signal by being applied with first and second N-bit control signals which are logic signals; and

an offset blocking circuit comprising a switch configured to turn off a current source of the slew rate compensation circuit by the offset control signal.

2 . The buffer circuit of claim 1 , wherein the slew rate compensation circuit comprises:

a first slew rate compensation circuit comprising a current source configured to provide the first slew rate compensation current to the load stage when a difference between the input voltage and the output voltage during a rising transition of the input voltage is equal to or more than a first reference voltage; and

a second slew rate compensation circuit comprising a current source configured to receive the second slew rate compensation current from the load stage when a difference between the input voltage and the output voltage during a falling transition of the input voltage is equal to or more than a second reference voltage.

3 . The buffer circuit of claim 2 , wherein the first slew rate compensation circuit comprises:

a first comparator comprising an NMOS transistor having a gate configured to receive the input voltage, a drain connected to a first node, and a source configured to receive the output voltage;

a first current source configured to generate a first slew rate compensation circuit operation current based on a difference between a power supply voltage and a voltage of the first node when the NMOS transistor of the first comparator performs a turn-on operation;

a first slew rate transistor configured to receive the first slew rate compensation circuit operation current through a gate terminal connected to the first node and perform a turn-on operation based on the first slew rate compensation circuit operation current; and

a second current source configured to generate the first slew rate compensation current based on the power supply voltage and provide the first slew rate compensation current to the load stage by the turn-on operation of the first slew rate transistor.

4 . The buffer circuit of claim 3 , wherein the second slew rate compensation circuit comprises:

a second comparator comprising a PMOS transistor having a gate configured to receive the input voltage, a drain connected to a second node, and a source configured to receive the output voltage;

a third current source configured to generate a second slew rate compensation circuit operation current based on a difference between a ground voltage and a voltage of the second node when the PMOS transistor of the second comparator performs a turn-on operation;

a second slew rate transistor configured to receive the second slew rate compensation circuit operation current through a gate terminal connected to the second node and perform a turn-on operation based on the second slew rate compensation circuit operation current; and

a fourth current source configured to generate the second slew rate compensation current based on the ground voltage and receive the second slew rate compensation current from the load stage by the turn-on operation of the second slew rate transistor.

5 . The buffer circuit of claim 2 , wherein the switch of the offset blocking circuit comprises:

a first switch having a gate configured to receive a first offset control signal, a source connected to a power supply voltage, and a drain connected to the first node of the first slew rate compensation circuit; and

a second switch having a gate configured to receive a second offset control signal, a drain connected to the second node of the second slew rate compensation circuit, and a source connected to a ground voltage.

6 . The buffer circuit of claim 5 , wherein the offset control signal output stage turns on the first switch by generating the first offset control signal of a low level after a first predetermined time elapses by the first N-bit control signal, and turns off the first switch by generating the first offset control signal of a high level after a second predetermined time elapses by the second N-bit control signal.

7 . The buffer circuit of claim 5 , wherein the offset control signal output stage turns on the second switch by generating the second offset control signal of a high level after a first predetermined time elapses by the first N-bit control signal, and turns off the second switch by generating the second offset control signal of a low level after a second predetermined time elapses by the second N-bit control signal.

8 . The buffer circuit of claim 5 , wherein the offset blocking circuit turns off a current source of the first slew rate compensation circuit by generating a level of a voltage equal to a level of a power supply voltage to the first node of the first slew rate compensation circuit, and turns off a current source of the second slew rate compensation circuit by generating a level of a voltage equal to a level of a ground voltage to the second node of the second slew rate compensation circuit.

9 . The buffer circuit of claim 1 , wherein the load stage comprises:

a first differential mirror circuit having a current mirror structure and a cascode structure, and configured to mirror the third and fourth differential currents and the first slew rate compensation current;

a second differential mirror circuit having a current mirror structure and a cascode structure, and configured to mirror the first and second differential currents and the second slew rate compensation current; and

a third bias circuit and a fourth bias circuit connected between the first differential mirror circuit and the second differential mirror circuit, and configured to control a static state operation and an amplification operation of the first differential mirror circuit and the second differential mirror circuit.

10 . The buffer circuit of claim 9 , wherein the first differential mirror circuit comprises first and second load stage PMOS transistors configured to perform a current mirroring operation, and third and fourth load stage PMOS transistors connected in series with the first and second load stage PMOS transistors, respectively, to form a cascode structure,

wherein the first load stage PMOS transistor has a gate in common with the second load stage PMOS transistor connected to the third bias circuit, a drain connected to a third node of the load stage connected between the first and third load stage PMOS transistors, and a source connected to a power supply voltage,

wherein the second load stage PMOS transistor has a gate in common with the first load stage PMOS transistor connected to the third bias circuit, a drain connected to a seventh node of the load stage connected between the second and fourth load stage PMOS transistors, and a source connected to the power supply voltage,

wherein the third load stage PMOS transistor has a gate connected between the third bias circuit and the first load stage PMOS transistor and configured to receive a second bias voltage, a drain connected to the third bias circuit and a fifth node of the load stage connected to the third bias circuit, and a source connected the third node, and

wherein the fourth load stage PMOS transistor has a gate connected between the fourth bias circuit and the second load stage PMOS transistor and configured to receive the second bias voltage, a drain connected to the fourth bias circuit, and a source connected to the seventh node.

11 . The buffer circuit of claim 10 , wherein the first differential mirror circuit is configured to receive the first slew rate compensation current through the third node from the slew rate compensation circuit.

12 . The buffer circuit of claim 9 , wherein the second differential mirror circuit comprises first and second load stage NMOS transistors configured to perform a current mirroring operation, and third and fourth load stage NMOS transistors connected in series with the first and second load stage NMOS transistors, respectively, to form a cascode structure,

wherein the first load stage NMOS transistor has a gate in common with the second load stage NMOS transistor connected to the third bias circuit, a drain connected to a fourth node of the load stage connected between the first and third load stage NMOS transistors, and a source connected to a ground voltage,

wherein the second load stage NMOS transistor has a gate in common with the first load stage NMOS transistor connected to the third bias circuit, a drain connected to an eighth node of the load stage connected between the second and fourth load stage NMOS transistors, and a source connected to the ground voltage,

wherein the third load stage NMOS transistor has a gate connected between the third bias circuit and the first load stage NMOS transistor and configured to receive a fifth bias voltage applied to gate terminals of the third and fourth load stage NMOS transistors, a drain connected to the third bias circuit, and a source connected to the fourth node, and

wherein the fourth load stage NMOS transistor has a gate connected between the fourth bias circuit and the second load stage NMOS transistor and configured to receive the fifth bias voltage, a drain connected to the fourth bias circuit, and a source connected to the eighth node.

13 . The buffer circuit of claim 12 , wherein the second differential mirror circuit is configured to provide the second slew rate compensation current from the fourth node to the slew rate compensation circuit.

14 . A buffer circuit for generating an output voltage based on an input voltage, comprising:

an input stage, a load stage, and an output stage, wherein the input stage is configured to provide first and second differential currents to the load stage based on a difference between the input voltage and the output voltage or receive third and fourth differential currents from the load stage,

wherein the load stage is configured to apply gate voltages to first and second output transistors of the output stage based on the first to fourth differential currents, and

wherein the output stage is configured to regulate the output voltage based on the gate voltages applied to the first and the second output transistors;

a slew rate compensation circuit configured to provide first slew rate compensation current to the load stage when a difference between a voltage level of the input voltage and a voltage level of the output voltage is equal to or more than a first reference voltage during a rising transition, and receive a second slew rate compensation current from the load stage when a difference between a voltage level of the input voltage and a voltage level of the output voltage is equal to or more than a second reference voltage during a falling transition;

an offset control signal output stage configured to receive first and second N-bit control signals which are logic signals to output an offset control signal; and

an offset blocking circuit comprising first and second switches configured to turn off a current source of the slew rate compensation circuit by the offset control signal.

15 . The buffer circuit of claim 14 , wherein the offset control signal output stage;

turns on the first switch by generating a first offset control signal of a low level after a first predetermined time elapses since the rising transition by the first N-bit control signal, and

turns off the first switch by generating the first offset control signal of a high level after a second predetermined time elapses since the rising transition by the second N-bit control signal.

16 . The buffer circuit of claim 14 , wherein the offset control signal output stage:

turns on the second switch by generating a second offset control signal of a high level after a first predetermined time elapses since the falling transition by the first N-bit control signal, and

turns off the second switch by generating the second offset control signal of a low level after a second predetermined time elapses since the falling transition by the second N-bit control signal.

17 . A method for controlling a buffer circuit, comprising:

comparing an input voltage to an output voltage of the buffer circuit;

providing or receiving a slew rate compensation current to or from a load stage when a difference between the input voltage and the output voltage is equal to or more than a reference voltage;

turning off transistors of the load stage based on the slew rate compensation current;

increasing or decreasing a gate voltage of an output transistor of an output stage connected to the load stage;

increasing a slew rate in a rising transition or a falling transition of the output voltage based on increase or decrease of the gate voltage of the output transistor;

receiving first and second N-bit control signals which are logic signals at an offset control signal output stage and outputting first and second offset control signals; and

controlling first and second switches of an offset blocking circuit configured to turn off a current source of a slew rate compensation circuit according to the first and second offset control signals.

18 . The method of claim 17 , further comprising:

providing a first slew rate compensation current from the slew rate compensation circuit to the load stage when a difference between the input voltage and the output voltage is equal to or more than a first reference voltage during the rising transition; and

receiving, at the slew rate compensation circuit, a second slew rate compensation current from the load stage when a difference between the input voltage and the output voltage is equal to or more than a second reference voltage during the falling transition.

19 . The method of claim 18 , further comprising:

turning on a first switch by generating a first offset control signal of a low level after a first predetermined time elapses since the rising transition by the first N-bit control signal;

blocking providing the first slew rate compensation current from the slew rate compensation circuit to the load stage; and

turning off the first switch by generating the first offset control signal of a high level after a second predetermined time elapses since the rising transition by the second N-bit control signal.

20 . The method of claim 18 , further comprising:

turning on a second switch by generating a second offset control signal of a high level after a first predetermined time elapses since the falling transition by the first N-bit control signal;

blocking providing the second slew rate compensation current from the load stage to the slew rate compensation circuit; and

turning off the second switch by generating the second offset control signal of a low level after a second predetermined time elapses since the falling transition by the second N-bit control signal.