Deterministic jitter compensation scheme for DTC timing path
In an example, a system includes an N divider coupled to an output of a low dropout regulator. The system also includes a load balancing circuit coupled to the N divider and configured to sink a load balancing current at the output of the low dropout regulator during one or more phases of the N divider. The system includes a switch coupled to the load balancing circuit and configured to connect the load balancing circuit to the output of the low dropout regulator during the one or more phases of the N divider.
1 . A fractional output divider (FOD), comprising:
a transistor having first and second terminals and a control terminal, the first terminal of the transistor coupled to a supply voltage terminal;
a frequency divider circuit having a first terminal coupled to the second terminal of the transistor, and having a second terminal, the frequency divider circuit configured to apply a first frequency divider value to an input signal in a first time period and apply a second frequency divider value to the input signal in a second time period, wherein the first frequency divider value is a first integer, and the second frequency divider value is a second integer and is greater than the first frequency divider value;
a load balancer having a first terminal, and having a second terminal coupled to the second terminal of the frequency divider circuit, the load balancer configured to provide a current;
a switch having a first terminal coupled to the second terminal of the transistor and having a second terminal coupled to the first terminal of the load balancer;
a controller configured to close the switch in the second time period and to open the switch in the first time period; and
a low dropout regulator having an output coupled to the control terminal of the transistor and having an input coupled to the second terminal of the transistor.
2 . The FOD of claim 1 , wherein the load balancer includes a switch network configured to set a magnitude of the current.
3 . The FOD of claim 1 , wherein the second frequency divider value is equal to the first frequency divider value plus one.
4 . The FOD of claim 1 , wherein the load balancer is configured to provide the current in the second time period.
5 . The FOD of claim 1 , wherein the controller is configured to open the switch throughout the first time period and to close the switch only a portion of the second time period to provide the current from the load balancer as a current pulse.
6 . The FOD of claim 1 , wherein a magnitude of the current is based at least in part on the first frequency divider value.
7 . The FOD of claim 1 , wherein a magnitude of the current is based at least in part on a temperature.
8 . The FOD of claim 1 , wherein the load balancer is configured to provide the current to regulate a voltage at an output of the low dropout regulator.
9 . The FOD of claim 1 , wherein the FOD includes a digital to time converter (DTC) and a multi-stage noise shaping (MASH) delta-sigma modulator.
10 . A system, comprising:
a frequency divider circuit configured to divide a frequency of an input signal by an integer N in a first time period and divide the frequency of the input signal by an integer N+1 in a second time period, the frequency divider circuit having first and second terminals;
a load balancer having a first terminal, and having a second terminal coupled to the second terminal of the frequency divider circuit, the load balancer configured to provide a current;
a switch having a first terminal, and having a second terminal coupled to the first terminal of the load balancer;
a low dropout regulator having an output, having a reference input, and having a second input;
a transistor having a control terminal coupled to the output of the low dropout regulator, having a first terminal coupled to a supply voltage terminal, and having a second terminal coupled to the second input of the low dropout regulator, to the first terminal of the frequency divider circuit, and to the second terminal of the transistor; and
a controller configured to close the switch in the second time period and to open the switch in the first time period.
11 . The system of claim 10 , wherein the load balancer is configured to provide the current to reduce a voltage at the output of the low dropout regulator.
12 . The system of claim 10 , wherein a magnitude of the current is based at least in part on a value of N.
13 . The system of claim 10 , wherein a magnitude of the current is based at least in part on a temperature.
14 . A system, comprising:
a pass transistor having a control terminal, a first terminal, and a second terminal;
a low dropout regulator having a reference input, a second input, and an output, the second input coupled to the second terminal of the pass transistor, the output coupled to the control terminal of the pass transistor;
a frequency divider circuit having a first terminal coupled to the second terminal of the pass transistor, and having a second terminal, the frequency divider circuit configured to apply a first frequency divider value to an input signal in a first time period and apply a second frequency divider value to the input signal in a second time period, wherein the second frequency divider value is greater than the first frequency divider value;
a sense transistor having a control terminal coupled to the output of the low dropout regulator, having a first terminal coupled to the first terminal of the pass transistor, and having a second terminal coupled to a test terminal;
a switch having a first terminal coupled to the second terminal of the pass transistor, to the second input of the low dropout regulator, and to the first terminal of the frequency divider circuit, and having a second terminal;
a load balancer having a first terminal coupled to the second terminal of the switch, and having a second terminal coupled to the second terminal of the frequency divider circuit, the load balancer configured to provide a current; and
a controller configured to open the switch throughout the first time period and to close the switch a portion of the second time period, and configured to set a magnitude of the current during the portion of the second time period.
15 . The system of claim 14 , wherein the controller is configured to sweep magnitudes of the current to select a first magnitude of current.
16 . The system of claim 15 , wherein the controller is configured to select the first magnitude of the current so that a current through the pass transistor during the first time period matches a current through the pass transistor during the second time period.
17 . The system of claim 16 , wherein the load balancer includes a switch network configurable to set the first magnitude of the current responsive to control of the controller.
18 . The system of claim 14 , wherein the controller is configured to set a magnitude of the current based at least in part on temperature.
19 . The system of claim 14 , further comprising a test instrument coupled to the test terminal and configured to receive a sense current, wherein the test instrument is configured to measure the sense current during one or more phases of the frequency divider circuit.
20 . The system of claim 14 , wherein the second frequency divider value is equal to the first frequency divider value plus one.