Charge pump circuit and phase-locked loop circuit

1 . A charge pump circuit comprising:

a current source;

a first current mirror including an input terminal connected to the current source;

a second current mirror including an input terminal connected to an output terminal of the first current mirror;

a third current mirror including an input terminal connected to a first output terminal of the second current mirror;

a fourth current mirror including an input terminal connected to a second output terminal of the second current mirror, and including an output terminal connected to a first node;

a first switch including a first end connected to a third output terminal of the second current mirror via a second node, and including a second end connected to the first node;

a second switch including a first end connected to an output terminal of the third current mirror via a third node, and including a second end connected to the first node; and

an output terminal connected to the first node.

2 . The charge pump circuit of claim 1 , wherein

each of the first current mirror, the third current mirror, and the fourth current mirror includes a transistor having a first conductivity type, and

the second current mirror includes a transistor having a second conductivity type that is different from the first conductivity type.

3 . The charge pump circuit of claim 2 , wherein

the transistor having the first conductivity type includes an N-type MOSFET, and

the transistor having the second conductivity type includes a P-type MOSFET.

4 . The charge pump circuit of claim 1 , wherein

the first current mirror includes:

a first transistor including a drain and a gate that are connected to the current source via a fourth node; and

a second transistor including a gate connected to the fourth node, and including a drain connected to the input terminal of the second current mirror via a fifth node,

the second current mirror includes:

a third transistor including a drain and a gate that are connected to the fifth node;

a fourth transistor including a drain connected to the input terminal of the fourth current mirror via a sixth node, and a gate connected to the fifth node; and

a fifth transistor including a drain connected to the second node, and a gate connected to the fifth node, and

the fourth current mirror includes:

a sixth transistor including a drain and a gate that are connected to the sixth node; and

a seventh transistor including a drain connected to the first node, and a gate connected to the sixth node.

5 . The charge pump circuit of claim 4 , wherein

a gate length of each of the first transistor, the second transistor and the third transistor is equal to or less than about ½ of a gate length of the seventh transistor, and

a gate width of each of the first transistor, the second transistor and the third transistor is equal to or less than about ½ of a gate width of the seventh transistor.

6 . The charge pump circuit of claim 4 , wherein

the second current mirror further includes an eighth transistor including a drain connected to the input terminal of the third current mirror via a seventh node, and including a gate connected to the fifth node, and

the third current mirror includes:

a ninth transistor including a drain and a gate that are connected to the seventh node; and

a tenth transistor including a drain connected to the third node, and a gate connected to the seventh node.

7 . The charge pump circuit of claim 6 , wherein

a gate length of each of the first transistor, the second transistor, the third transistor, the eighth transistor and the ninth transistor is equal to or less than about ½ of a gate length of the seventh transistor, and

a gate width of each of the first transistor, the second transistor, the third transistor, the eighth transistor and the ninth transistor is equal to or less than about ½ of a gate width of the seventh transistor.

8 . The charge pump circuit of claim 1 , further comprising:

a third switch including a first end connected to the second node, and including a second end; and

a first resistor including one end connected to the second end of the third switch.

9 . The charge pump circuit of claim 8 , wherein each of the first switch and the third switch includes a transistor.

10 . The charge pump circuit of claim 8 , wherein

the third switch is configured to be in an OFF state, in a case where the first switch is in an ON state, and

the third switch is configured to be in an ON state, in a case where the first switch is in an OFF state.

11 . The charge pump circuit of claim 8 , further comprising:

a fourth switch including a first end connected to the third node, and including a second end; and

a second resistor including one end connected to the second end of the fourth switch.

12 . The charge pump circuit of claim 11 , wherein

each of the second switch and the fourth switch includes a transistor having a first conductivity type, and

each of the first switch and the third switch includes a transistor having a second conductivity type that is different from the first conductivity type.

13 . The charge pump circuit of claim 12 , wherein

the transistor having the first conductivity type includes an N-type MOSFET, and

the transistor having the second conductivity type includes a P-type MOSFET.

14 . The charge pump circuit of claim 11 , wherein

the third switch is configured to be in an OFF state, in a case where the first switch is in an ON state,

the third switch is configured to be in an ON state, in a case where the first switch is in an OFF state,

the fourth switch is configured to be in an OFF state, in a case where the second switch is in an ON state, and

the fourth switch is configured to be in an ON state, in a case where the second switch is in an OFF state.

15 . A phase-locked loop circuit comprising:

the charge pump circuit of claim 1 ;

a phase frequency detector connected to the charge pump circuit;

a loop filter connected to the charge pump circuit;

a voltage-controlled oscillator connected to the loop filter; and

a divider connected to the phase frequency detector and the voltage-controlled oscillator.

16 . The phase-locked loop circuit of claim 15 , wherein the charge pump circuit is configured to:

output a first current to the loop filter via the output terminal in a case where the first switch is in an ON state; and

input a second current from the loop filter via the output terminal in a case where the first switch is in an OFF state.

17 . The phase-locked loop circuit of claim 16 , wherein in a first state, a total amount of charge based on the first current that is output from the charge pump circuit to the loop filter during one cycle of a signal that is input to the phase frequency detector is substantially equal to a total amount of charge based on the second current that is input from the loop filter to the charge pump circuit during the cycle.

18 . The phase-locked loop circuit of claim 15 , wherein the phase frequency detector is configured to control the first switch by applying a voltage to the first switch.

19 . The phase-locked loop circuit of claim 15 , wherein

each of the first current mirror, the third current mirror, and the fourth current mirror includes a transistor having a first conductivity type, and

the second current mirror includes a transistor having a second conductivity type that is different from the first conductivity type.

20 . The phase-locked loop circuit of claim 19 , wherein

the transistor having the first conductivity type includes an N-type MOSFET, and

the transistor having the second conductivity type includes a P-type MOSFET.