IP Library › Granted Patent US 12676628
Granted Patent B2
US 12676628 · App. 18/597,217 · Granted Jul 7, 2026

Voltage-to-time converters and methods of operating same

Inventors: Jueon Kim (Suwon-si, KR); Taehyoung Kim (Singapore, SG); Donghyun Yoon (Singapore, SG); Myoungbo Kwak (Suwon-si, KR); Jaewoo Park (Suwon-si, KR); Youngdon Choi (Suwon-si, KR); Junghwan Choi (Suwon-si, KR)
Assignees: Samsung Electronics Co., Ltd.; Nanyang Technological University
H03M1/50
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Quick Facts
Patent No.
US 12676628
App. No.
18/597,217
Granted
Jul 7, 2026
Kind
B2
Abstract

A voltage-to-time converter (VTC) includes: a first inverter electrically connected between a first node, to which a clock signal is applied, and a second node, a first buffer electrically connected to the second node and to output a first output signal, a second inverter electrically connected between a third node, to which the clock signal is applied, and a fourth node, a second buffer electrically connected to the fourth node to output a second output signal, a first linearization circuit configured to receive a first input signal and electrically connected between the first node and the second node, and a second linearization circuit configured to receive a second input signal and electrically connected between the third node and the fourth node.

Claims (68)

1 . A voltage-to-time converter (VTC), comprising:

a first inverter electrically connected between a first node to which a clock signal is applied and a second node;

a first buffer electrically connected to the second node and to output a first output signal;

a second inverter electrically connected between a third node to which the clock signal is applied and a fourth node; and

a second buffer electrically connected to the fourth node to output a second output signal;

a first linearization circuit configured to receive a first input signal and electrically connected between the first node and the second node; and

a second linearization circuit configured to receive a second input signal and electrically connected between the third node and the fourth node.

2 . The VTC of claim 1 , wherein an on-resistance of a transistor included in the first inverter is inversely proportional to a variation in delay time between the first input signal and the first output signal.

3 . The VTC of claim 1 , wherein an on-resistance of a transistor included in the first linearization circuit is inversely proportional to a variation in delay time between the first input signal and the first output signal.

4 . The VTC of claim 1 , wherein the first linearization circuit comprises: a first P-type transistor having a drain terminal electrically connected to the first node, a source terminal electrically connected to the second node, and a gate terminal responsive to the first input signal as an input value.

5 . The VTC of claim 1 , wherein the first input signal and the second input signal are related as a differential signal pair.

6 . The VTC of claim 1 , wherein the first linearization circuit comprises:

a first P-type transistor having a source terminal electrically connected to the second node, a drain terminal electrically connected to the first node, and a gate terminal responsive to the first input signal as an input value; and

a first N-type transistor having a source terminal electrically connected to the second node, a drain terminal electrically connected to the first node, and a gate terminal responsive to a reference voltage as an input value.

7 . The VTC of claim 1 , wherein the first input signal and the second input signal are an equivalent single-ended signal.

8 . The VTC of claim 1 , further comprising:

a first VTC gain control transistor;

wherein the first inverter comprises:

a second P-type transistor having a source terminal to which a positive supply voltage is applied, a gate terminal electrically connected to the first node, and a drain terminal electrically connected to the second node; and

a second N-type transistor having a gate terminal electrically connected to the first node, and a drain terminal electrically connected to the second node; and

wherein the first VTC gain control transistor has a gate terminal to which a VTC gain control voltage is applied, a drain terminal electrically connected to a source terminal of the second N-type transistor, and a source terminal to which a ground voltage is applied.

9 . A time-based (TB) receiver, comprising:

a voltage-to-time converter (VTC) configured to receive an input signal and output two output signals having different delay times that reflect a data value of the input signal, which is based on a delay time difference between the two output signals;

a compensation circuit configured to receive the two output signals as a pair of input values, and output compensation signals by removing noise in the form of inter-symbol interference (ISI) from the pair of input values; and

a decoder configured to reconstruct a digital signal from the compensation signals; and

wherein on-resistances of transistors included in the VTC are inversely proportional to corresponding delay times between the input signal and the two output signals.

10 . The TB receiver of claim 9 ,

wherein the input signal includes a first input signal and a second input signal; and

wherein VTC comprises:

a first inverter electrically connected between a first node to which a clock signal is applied, and a second node;

a first buffer electrically connected to the second node, and to output a first output signal;

a second inverter electrically connected between a third node to which the clock signal is applied, and a fourth node;

a second buffer electrically connected to the fourth node, and to output a second output signal;

a first linearization circuit configured to receive the first input signal and electrically connected between the first node and the second node; and

a second linearization circuit configured to receive the second input signal and electrically connected between the third node and the fourth node.

11 . The TB receiver of claim 10 , wherein the first linearization circuit comprises a first P-type transistor having a drain terminal electrically connected to the first node, a source terminal electrically connected to the second node, and a gate terminal, which is configured to receive the first input signal as an input value.

12 . The TB receiver of claim 10 , wherein the first input signal and the second input signal are one differential signal pair.

13 . The TB receiver of claim 10 , wherein the first linearization circuit comprises:

a first P-type transistor having a gate terminal configured to receive the first input signal as an input value, a source terminal electrically connected to the second node, and a drain terminal electrically connected to the first node; and

a first N-type transistor having a gate terminal configured to receive a reference voltage as an input value, a source terminal electrically connected to the second node, and a drain terminal electrically connected to the first node.

14 . The TB receiver of claim 10 , wherein the first and second input signals are equivalent signals.

15 . The TB receiver of claim 10 , further comprising:

a first VTC gain control transistor having a gate terminal configured to receive a VTC gain control voltage, and a source terminal to which a ground voltage is applied; and

wherein the first inverter comprises:

a second P-type transistor having a source terminal to which a positive supply voltage is applied, a gate terminal electrically connected to the first node, and a drain terminal electrically connected to the second node; and

a second N-type transistor having a gate terminal electrically connected to the first node, a drain terminal electrically connected to the second node, and a source terminal electrically connected to a drain terminal of the first VTC gain control transistor.

16 . A transmission and reception system, comprising:

a transmitter configured to output a transmission signal based on multi-level signaling; and

a time-based (TB) receiver responsive to the transmission signal, said TB receiver comprising:

a voltage-to-time converter (VTC) configured to receive an input signal and output two output signals having different delay times so as to identify a data value of the input signal based on a delay time difference of the output signals, said VTC including transistors having on-resistances that are inversely proportional to corresponding delay times between the transmission signal and the output signals.

17 . The system of claim 16 ,

wherein the transmission signal includes a first input signal and a second input signal; and

wherein the VTC comprises:

a first inverter electrically connected between a first node to which a clock signal is applied and a second node;

a first buffer electrically connected to the second node, and to output a first output signal;

a second inverter electrically connected between a third node to which the clock signal is applied and a fourth node;

a second buffer electrically connected to the fourth node, and to output a second output signal;

a first linearization circuit configured to receive the first input signal, and electrically connected between the first node and the second node; and

a second linearization circuit configured to receive the second input signal, and electrically connected between the third node and the fourth node.

18 . The system of claim 17 , wherein the first linearization circuit comprises a first P-type transistor having a drain terminal electrically connected to the first node, a source terminal electrically connected to the second node, and a gate terminal configured to receive the first input signal as an input value.

19 . The system of claim 17 , wherein the first linearization circuit comprises:

a first P-type transistor having a gate terminal configured to receive the first input signal as an input value, a source terminal electrically connected to the second node, and a drain terminal electrically connected to the first node; and

a first N-type transistor having a gate terminal configured to receive a reference voltage as an input value, a source terminal electrically connected to the second node, and a drain terminal electrically connected to the first node.

20 . The system of claim 17 , further comprising:

a first VTC gain control transistor having a gate terminal to which a VTC gain control voltage is applied, and a source terminal to which a ground voltage is applied; and

wherein the first inverter comprises:

a second P-type transistor having a source terminal to which a positive supply voltage is applied, a gate terminal electrically connected to the first node, and a drain terminal electrically connected to the second node; and

a second N-type transistor having a gate terminal electrically connected to the first node, a drain terminal electrically connected to the second node, and a source terminal electrically connected to a drain terminal of the VTC gain control transistor.