Digital-to-analog converter and apparatus including the same

1 . A digital-to-analog converter (DAC) comprising:

a current cell matrix comprising a plurality of first current cells configured to generate an analog signal; and

a path array comprising a plurality of path groups configured to control the plurality of first current cells to be turned on or off,

wherein any one of the plurality of path groups comprises:

an alternative path comprising a first latch circuit configured to transmit dummy data;

a normal path comprising a second latch circuit configured to transmit normal data; and

a path selector configured to control any one of the dummy data and the normal data to toggle based on a pattern of digital data corresponding to the normal data.

2 . The DAC of claim 1 , wherein the alternative path further comprises:

a data toggling circuit configured to output the dummy data selectively toggling based on a clock signal and a path selection signal received from the path selector to the first latch circuit; and

a first clock output circuit configured to selectively output a dummy clock signal to the first latch circuit based on the clock signal and the path selection signal.

3 . The DAC of claim 2 , wherein, when the path selection signal is generated based on a current level and a previous level of the digital data being the same, the data toggling circuit is configured to output the dummy data toggling according to the clock signal, and the first clock output circuit is configured to output the dummy clock signal.

4 . The DAC of claim 2 , wherein, when the path selection signal is generated based on a current level and a previous level of the digital data being different from each other, the data toggling circuit is configured to output the dummy data that is maintained at a certain level, and the first clock output circuit is configured to block output of the dummy clock signal.

5 . The DAC of claim 1 , wherein the normal path further comprises:

a data output circuit configured to output the normal data to the second latch circuit based on a clock signal and the digital data; and

a second clock output circuit configured to selectively output a clock output signal to the second latch circuit based on the clock signal and a path selection signal received from the path selector.

6 . The DAC of claim 5 , wherein a phase of the clock output signal is different from a phase of the clock signal, or a magnitude of the clock output signal is different from a magnitude of the clock signal.

7 . The DAC of claim 1 , wherein an output terminal of the first latch circuit floats, and

wherein an output terminal of the second latch circuit is connected to any one of the plurality of first current cells.

8 . The DAC of claim 1 , wherein the path selector comprises:

a comparison circuit configured to compare a current level of the digital data with a previous level of the digital data and generate a comparison result signal; and

a path selection signal generation circuit configured to generate a first path selection signal and a second path selection signal for respectively controlling the alternative path and the normal path based on the comparison result signal and a clock signal.

9 . The DAC of claim 8 , wherein a phase of the clock signal leads a phase of a clock signal provided to the alternative path and the normal path.

10 . The DAC of claim 8 , wherein the path selection signal generation circuit is further configured to be activated or deactivated according to an operation mode of the DAC.

11 . The DAC of claim 1 , wherein the current cell matrix further comprises a plurality of second current cells configured to generate the analog signal, and

wherein the path array further comprises a plurality of normal paths configured to control the plurality of second current cells to be turned or off.

12 . The DAC of claim 1 , further comprising a data decoder configured to decode n-ary digital data into the digital data based on a thermometer code.

13 . A digital-to-analog converter (DAC) configured to convert a digital signal comprising a plurality of pieces of digital data into an analog signal, the DAC comprising:

a current cell matrix comprising a plurality of current cells configured to generate the analog signal;

a first alternative path comprising a first latch circuit configured to create a toggle in first dummy data; and

a first normal path comprising a second latch circuit configured to control a first current cell among the plurality of current cells to be turned on or off,

wherein the first alternative path further comprises a first clock output circuit configured to selectively output a dummy clock signal used for the toggle to the first latch circuit based on a pattern of first digital data among the plurality of pieces of digital data.

14 . The DAC of claim 13 , wherein an output terminal of the first latch circuit is configured to float, and

wherein an output terminal of the second latch circuit is configured to be provided to a switch included in the first current cell.

15 . The DAC of claim 13 , wherein the first normal path further comprises a second clock output circuit configured to selectively output a clock output signal to the second latch circuit based on the pattern of the first digital data.

16 . The DAC of claim 13 , further comprising a first path selector configured to control the first alternative path to allow the first dummy data transmitted to the first latch circuit to toggle when a current level of the first digital data is same as a previous level of the first digital data and control the first normal path to allow normal data transmitted to the second latch circuit and provided as a cell control signal to the first current cell to toggle when the current level of the first digital data is different from the previous level of the first digital data,

wherein the normal data corresponds to the first digital data.

17 . The DAC of claim 16 , wherein the first normal path further comprises a flip-flop comprising an input terminal configured to receive the first digital data and an output terminal configured to output the first digital data in response to a first clock signal, and

wherein the first path selector is further configured to receive the current level of the first digital data from the input terminal of the flip-flop and receive the previous level of the first digital data from the output terminal of the flip-flop.

18 . The DAC of claim 17 , wherein the first path selector is further configured to compare the current level of the first digital data with the previous level of the first digital data in response to a second clock signal having a phase leading a phase of the first clock signal and control at least one of the first alternative path and the first normal path based on a comparison result.

19 . The DAC of claim 16 , wherein at least one of the first alternative path and the first path selector is deactivated in a low-power mode of the DAC.

20 . A digital-to-analog converter (DAC) comprising:

a current cell matrix comprising a plurality of current cells configured to generate an analog signal;

a normal path connected to a first current cell among the plurality of current cells and configured to block output of a clock output signal to a latch circuit to which normal data is transmitted in a period in which a level of the normal data for turning on/off the first current cell is maintained; and

an alternative path configured to block output of a dummy clock signal to a latch circuit to which dummy data is transmitted in a period in which the normal data toggles,

wherein a period in which the normal data toggles in the normal path is different from a period in which the dummy data toggles in the alternative path.