IP Library › Granted Patent US 12676696

Granted Patent B2

US 12676696 · App. 18/424,339 · Granted Jul 7, 2026

Decoding method and apparatus

Inventor: Chengmin Zhang (Dongguan, CN)

Assignee: Huawei Technologies Co., Ltd.

H04L1/0036 H04L1/0015

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Quick Facts

Patent No.: US 12676696
App. No.: 18/424,339
Granted: Jul 7, 2026
Kind: B2

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Abstract

A decoding method and an apparatus are provided. A decoder includes a type detection module, a decoding and prediction module, a state determining module, and an output processing module. The type detection module is configured to detect a type of a to-be-decoded code block. The decoding and prediction module is configured to decode the to-be-decoded code block, and obtain a predicted decoding mode of the to-be-decoded code block. The state determining module is configured to select a decoding mode from the predicted decoding mode of the to-be-decoded code block. The output processing module is configured to update a decoding result based on the decoding mode selected by the state determining module. The decoder further includes a delay device, configured to delay outputting received data by at least one clock cycle.

Claims (55)

1 . A decoder, wherein the decoder comprises: a type detector, configured to detect a type of N to-be-decoded code blocks, wherein the N to-be-decoded code blocks are arranged in sequence, and N is an integer greater than or equal to 1;

a decoding and predicting circuit, configured to: decode the N to-be-decoded code blocks based on the type of the N to-be-decoded code blocks, to obtain a decoding result of the N to-be-decoded code blocks; and obtain a predicted decoding mode of at least one code block of the N to-be-decoded code blocks by predicting, for a next to-be-decoded code block of a current to-be-decoded code block, possible decoding modes of the next to-be-decoded block;

a state determiner, configured to select a decoding mode from a predicted decoding mode of each of the at least one code block; and

an output processor, configured to update the decoding result based on the decoding mode, to obtain and output media independent interface information corresponding to the N to-be-decoded code blocks, wherein

the decoder further comprises a delay circuit, configured to delay outputting received data by at least one clock cycle, wherein

the type detector sends the type of the N to-be-decoded code blocks to the decoding and predicting circuit via the delay circuit;

the decoding and predicting circuit sends the predicted decoding mode to the state determiner and the decoding result of the N to-be-decoded code blocks to the output processor via the delay circuit; or the state determiner sends the decoding mode to the output processor via the delay circuit.

2 . The decoder according to claim 1 , wherein the state determiner is configured to:

select a decoding mode from a predicted decoding mode of a first to-be-decoded code block based on a type of the first to-be-decoded code block and a type of a next code block of the first to-be-decoded code block, wherein the first to-be-decoded code block is any one of the at least one code block.

3 . The decoder according to claim 2 , wherein the output processor is configured to:

in response to a decoding mode used by the decoding and predicting circuit for the first to-be-decoded code block being different from the decoding mode selected by the state determiner from the predicted decoding mode of the first to-be-decoded code block, update a decoding result of the first to-be-decoded code block based on the decoding mode selected by the state determiner from the predicted decoding mode of the first to-be-decoded code block, wherein the first to-be-decoded code block is any one of the at least one code block.

4 . The decoder according to claim 2 , wherein the output processor is configured to:

in response to the decoding mode selected from the predicted decoding mode of the first to-be-decoded code block being a decoding mode used in an error state, update a decoding result of the first to-be-decoded code block to an error code, wherein the first to-be-decoded code block is any one of the at least one code block.

5 . The decoder according to claim 2 , wherein the output processor is configured to:

in response to the decoding mode selected from the predicted decoding mode of the first to-be-decoded code block being a decoding mode used in a low-power state, update a decoding result of the first to-be-decoded code block to a low-power control code, wherein the first to-be-decoded code block is any one of the at least one code block.

6 . The decoder according to claim 1 , wherein the type detector comprises N type subdetectors, and the N type subdetectors are in a one-to-one correspondence with the N to-be-decoded code blocks;

the decoding and predicting circuit comprises N decoding subcircuits and N predicting subcircuits, the N decoding subcircuits are in a one-to-one correspondence with the N to-be-decoded code blocks, and the N predicting subcircuits are in a one-to-one correspondence with the N to-be-decoded code blocks; and

the output processor comprises N output subprocessors, and the N output subprocessors are in a one-to-one correspondence with the N to-be-decoded code blocks.

7 . The decoder according to claim 6 , wherein the N type subdetectors run in parallel, the N decoding subcircuits run in parallel, the N predicting subcircuits run in parallel, and the N output subprocessors run in parallel.

8 . The decoder according to claim 1 , wherein the to-be-decoded code block is a 66-bit block descrambled by a physical coding sublayer (PCS), the 66-bit block comprises a 2-bit synchronization header and a 64-bit payload, the 64-bit payload comprises 8-bit block type information and 56-bit data, and the media independent interface information comprises 64-bit 10 Gigabit Media Independent Interface (XGMII)/25 Gigabit Media Independent Interface (XXVGMII) interface data and 8-bit XGMII/XXVGMII interface control information.

9 . A decoding method, wherein the method comprises: detecting a type of N to-be-decoded code blocks, wherein N is an integer greater than or equal to 1;

decoding the N to-be-decoded code blocks based on the type of the N to-be-decoded code blocks, to obtain a decoding result of the N to-be-decoded code blocks; and obtaining a predicted decoding mode of at least one code block of the N to-be-decoded code blocks by predicting, for a next to-be-decoded code block of a current to-be-decoded code block, possible decoding modes of the next to-be-decoded block;

selecting a decoding mode from a predicted decoding mode of each of the at least one code block; and

updating the decoding result based on the decoding mode, to obtain and output media independent interface information corresponding to the N to-be-decoded code blocks, wherein

the method further comprises at least one of the following operations:

delaying outputting the type of the N to-be-decoded code blocks by at least one clock cycle;

delaying outputting the predicted decoding mode and the decoding result of the N to-be-decoded code blocks by the at least one clock cycle; and

delaying outputting, by the at least one clock cycle, the decoding mode selected from the predicted decoding mode of each of the at least one code block.

10 . The method according to claim 9 , wherein the obtaining the predicted decoding mode of the at least one code block of the N to-be-decoded code blocks comprises:

selecting a decoding mode from a predicted decoding mode of a first to-be-decoded code block based on a type of the first to-be-decoded code block and a type of a next code block of the first to-be-decoded code block, wherein the first to-be-decoded code block is any one of the at least one code block.

11 . The method according to claim 10 , wherein the updating the decoding result based on the decoding mode selected from the predicted decoding mode of each of the at least one code block comprises:

in response to a decoding mode used by a decoding and predicting circuit for the first to-be-decoded code block being different from the decoding mode selected by a state determiner from the predicted decoding mode of the first to-be-decoded code block, updating a decoding result of the first to-be-decoded code block based on the decoding mode selected by the state determiner from the predicted decoding mode of the first to-be-decoded code block, wherein the first to-be-decoded code block is any one of the at least one code block.

12 . The method according to claim 10 , wherein updating the decoding result based on the decoding mode selected from the predicted decoding mode of each of a part of the code blocks comprises:

in response to the decoding mode selected from the predicted decoding mode of the first to-be-decoded code block being a decoding mode used in an error state, updating a decoding result of the first to-be-decoded code block to an error code, wherein the first to-be-decoded code block is any one of the at least one code block.

13 . The method according to claim 10 , wherein updating the decoding result based on the decoding mode selected from the predicted decoding mode of each of a part of the code blocks comprises:

in response to the decoding mode selected from the predicted decoding mode of the first to-be-decoded code block being a decoding mode used in a low-power state, updating a decoding result of the first to-be-decoded code block to a low-power control code, wherein the first to-be-decoded code block is any one of the at least one code block.

14 . The method according to claim 9 , wherein the to-be-decoded code block is a 66-bit block descrambled by a physical coding sublayer (PCS), the 66-bit block comprises a 2-bit synchronization header and a 64-bit payload, the 64-bit payload comprises 8-bit block type information and 56-bit data, and the media independent interface information comprises 64-bit 10 Gigabit Media Independent Interface (XGMII)/25 Gigabit Media Independent Interface (XXVGMII) interface data and 8-bit XGMII/XXVGMII interface control information.

15 . An electronic device, wherein the electronic device comprises one or more processors and one or more memories, the one or more memories store one or more computer programs, the one or more computer programs comprise instructions, and when the instructions are executed by the one or more processors, cause the electronic device to perform:

detecting a type of N to-be-decoded code blocks, wherein N is an integer greater than or equal to 1;

selecting a decoding mode from a predicted decoding mode of each of the at least one code block; and

updating the decoding result based on the decoding mode, to obtain and output media independent interface information corresponding to the N to-be-decoded code blocks, wherein

the electronic device is further caused to perform at least one of the following operations:

delaying outputting the type of the N to-be-decoded code blocks by at least one clock cycle;

delaying outputting the predicted decoding mode and the decoding result of the N to-be-decoded code blocks by the at least one clock cycle; and

delaying outputting, by the at least one clock cycle, the decoding mode selected from the predicted decoding mode of each of the at least one code block.

16 . The electronic device according to claim 15 , wherein the obtaining the predicted decoding mode of the at least one code block of the N to-be-decoded code blocks comprises the electronic device is caused to perform:

17 . The electronic device according to claim 16 , wherein the updating the decoding result based on the decoding mode selected from the predicted decoding mode of each of the at least one code block comprises the electronic device is caused to perform:

18 . The electronic device according to claim 16 , wherein updating the decoding result based on the decoding mode selected from the predicted decoding mode of each of a part of the code blocks comprises the electronic device is caused to perform:

19 . The electronic device according to claim 16 , wherein updating the decoding result based on the decoding mode selected from the predicted decoding mode of each of a part of the code blocks comprises the electronic device is caused to perform:

20 . The electronic device according to claim 15 , wherein the to-be-decoded code block is a 66-bit block descrambled by a physical coding sublayer (PCS), the 66-bit block comprises a 2-bit synchronization header and a 64-bit payload, the 64-bit payload comprises 8-bit block type information and 56-bit data, and the media independent interface information comprises 64-bit 10 Gigabit Media Independent Interface (XGMII)/25 Gigabit Media Independent Interface (XXVGMII) interface data and 8-bit XGMII/XXVGMII interface control information.