Dynamic frequency supported time division multiplexing interface
A time division multiplexing (TDM) device includes a first first-in-first-out (FIFO) circuit configured to receive a user clock signal and a user data signal from a plurality of inputs, a transmitter circuit operatively coupled to the first FIFO circuit in a fast clock domain, the transmitter circuit including one or more multiplexing state machines, the one or more multiplexing state machines configured to receive a plurality of input signals from the plurality of inputs, multiplexing the input signals to form a multiplexed signal, and transmitting the multiplexed signal using a fast clock, a receiver circuit including one or more demultiplexing state machines, the one or more demultiplexing state machines configured to receive the multiplexed signal, and a second FIFO circuit configured to output the user data signal to the plurality of outputs.
1 . A device, comprising:
a first first-in-first-out (FIFO) circuit to receive a user clock signal and a user data signal from a plurality of inputs;
a transmitter circuit operatively coupled to the first FIFO circuit in a fast clock domain, the transmitter circuit comprising one or more multiplexing state machines to combine the user data signal from the plurality of inputs to form a multiplexed signal;
a receiver circuit comprising one or more demultiplexing state machines, the one or more demultiplexing state machines to receive the multiplexed signal;
a second FIFO circuit to output the user data signal to a plurality of outputs with respect to a user clock in the receiver circuit; and
an asynchronous frequency control circuit coupled to the second FIFO circuit, the asynchronous frequency control circuit comprising a plurality of flip flops to delay the user data signal output by the second FIFO circuit.
2 . The device of claim 1 , wherein the transmitter circuit further comprises one or more synchronizers, the one or more synchronizers configured to introduce a delay in a first signal indicating an empty state of the first FIFO circuit.
3 . The device of claim 2 , wherein the delay is determined based on a latency between the one or more multiplexing state machines and the one or more demultiplexing state machines.
4 . The device of claim 2 ,
wherein the asynchronous frequency control circuit causes the delay in the first signal output by the second FIFO circuit.
5 . The device of claim 1 , further comprising:
a first gigabit transceiver interface socket to receive signals from the transmitter circuit; and
a second gigabit transceiver interface socket operatively coupled to the first gigabit transceiver interface socket via a high-speed line, the second gigabit transceiver interface socket configured to transmit the multiplexed signal to the receiver circuit.
6 . The device of claim 1 , further comprising:
a logic circuit with a loopback plug inserted into a port or interface of the device, wherein the loopback plug routes a signal back to the device, thereby creating a loop.
7 . The device of claim 6 , wherein the logic circuit comprises at least one or more of a combinational loopback logic and a handshake user logic.
8 . The device of claim 1 , wherein the one or more demultiplexing state machines comprise one or more serial in parallel out (SIPO) shift registers coupled to one or more parallel in parallel out (PIPO) storage registers.
9 . A method, comprising:
receiving, by a first first-in-first-out (FIFO) circuit, a user clock signal and a user data signal from a plurality of inputs;
multiplexing, by a transmitter circuit coupled to the first FIFO circuit in a fast clock domain, the user data signal from the plurality of inputs to form a multiplexed signal, the transmitter circuit comprising one or more multiplexing state machines;
receiving, by a receiver circuit coupled to the transmitter circuit, the multiplexed signal, the receiver circuit comprising one or more demultiplexing state machines;
outputting, by a second FIFO circuit coupled to the receiver circuit, the user data signal to a plurality of outputs with respect to a user clock in the receiver circuit; and
delaying, by an asynchronous frequency control circuit coupled to the second FIFO circuit, the user data signal output by the second FIFO circuit, wherein the asynchronous frequency control circuit comprises a plurality of flip flops to cause the delay.
10 . The method of claim 9 , further comprising:
introducing, by one or more synchronizers in the transmitter circuit, a delay in first signal indicating an empty state of the first FIFO circuit.
11 . The method of claim 10 , wherein the delay is determined based on a latency between the one or more multiplexing state machines and the one or more demultiplexing state machines.
12 . The method of claim 10 , further comprising:
causing the delay, by the asynchronous frequency control circuit coupled to the receiver circuit.
13 . The method of claim 9 , further comprising:
receiving, by a first gigabit transceiver interface socket, the user data signal from the transmitter circuit; and
transmitting, by a second gigabit transceiver interface socket operatively coupled to the first gigabit transceiver interface socket via a high-speed line, the multiplexed signal to the receiver circuit.
14 . The method of claim 9 , further comprising:
providing a logic circuit with a loopback plug inserted into the receiver circuit, wherein the loopback plug routes a signal back to the first FIFO circuit, thereby creating a loop.
15 . The method of claim 14 , wherein the logic circuit comprises at least one of a combinational loopback logic and a handshake-based user logic.
16 . A time division multiplexing (TDM) device, comprising:
a first first-in-first-out (FIFO) circuit to receive a user clock signal and a user data signal from a plurality of inputs;
a transmitter circuit operatively coupled to the first FIFO circuit in a fast clock domain, the transmitter circuit comprising one or more multiplexing state machines, the one or more multiplexing state machines to receive the user data signal from the plurality of inputs, multiplexing the user data signals to form a multiplexed signal, and transmitting the multiplexed signal on a single line using a fast clock, wherein the transmitter circuit further comprises one or more synchronizers, the one or more synchronizers to introduce a delay in a first signal indicating an empty state of the first FIFO circuit;
a receiver circuit to receive the multiplexed signal;
a second FIFO circuit to output the user data signal to a plurality of outputs with respect to a user clock in the receiver circuit; and
an asynchronous frequency control circuit comprising a plurality of flip flops to cause the delay in the user data signal output by the second FIFO circuit.
17 . The TDM device of claim 16 ,
wherein the receiver circuit comprises one or more demultiplexing state machines.
18 . The TDM device of claim 17 , wherein the one or more multiplexing state machines are coupled to an AND/OR/BYPASS control circuit or the one or more synchronizers are shared by two or more multiplexing state machines, the control circuit configured to transmit the multiplexed signal to the receiver circuit.
19 . The TDM device of claim 17 , wherein the one or more demultiplexing state machines are coupled to an AND control circuit, the AND control circuit configured to output the multiplexed signal to the second FIFO circuit.
20 . The TDM device of claim 17 ,
wherein the asynchronous frequency control circuit causes the delay in the first signal output by the second FIFO circuit.