IP Library Granted Patent US 12676763
Granted Patent B2
US 12676763 · App. 18/123,595 · Granted Jul 7, 2026

Systems and methods using physically unclonable functions without a challenge-response database

Inventors: Daniel Gauthier (Hilliard, OH); Andrew Joseph Pomerance (Alexandria, VA)
Assignee: Ohio State Innovation Foundation
H04L9/3278H04L9/0656H04L9/3236
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Quick Facts
Patent No.
US 12676763
App. No.
18/123,595
Granted
Jul 7, 2026
Kind
B2
Abstract

Described herein are methods and systems implementing physically unclonable functions (PUFs). An example method includes: inputting a first challenge bit string into a first PUF; capturing a first response bit string from the first PUF; inputting a second challenge bit string into a second PUF; capturing a second response bit string from the second PUF; performing a hash operation on the first response bit string and the second response bit string, the hash operation generating a hashed-response bit string; and storing the first and second challenge bit strings and the hashed-response bit string in a first database.

Claims (45)

1 . A method, comprising:

inputting a first challenge bit string into a first physically unclonable function (PUF);

capturing a first response bit string from the first PUF;

inputting a second challenge bit string into a second PUF;

capturing a second response bit string from the second PUF;

performing a hash operation on the first response bit string of the first PUF and the second response bit string of the second PUF, the hash operation generating a hashed-response bit string; and

storing the first and second challenge bit strings and the hashed-response bit string in a first database.

2 . The method of claim 1 , further comprising deleting the first response bit string and the second response bit string after performing the hash operation.

3 . The method of claim 1 , wherein the step of performing the hash operation comprises performing an XOR operation on the first response bit string of the first PUF and the second response bit string of the second PUF.

4 . The method of claim 1 , further comprising:

inputting a third challenge bit string into the first PUF;

capturing a third response bit string from the first PUF;

inputting a fourth challenge bit string into a third PUF;

capturing a fourth response bit string from the third PUF;

performing a second hash operation on the third response bit string of the first PUF and the fourth response bit string of the third PUF, the hash operation generating a second hashed-response bit string; and

storing the third and fourth challenge bit strings and the second hashed-response bit string in a second database.

5 . The method of claim 4 , wherein at least one of the first PUF, the second PUF, and the third PUF is embodied as an integrated circuit (IC) chip.

6 . The method of claim 5 , wherein the IC chip is a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC).

7 . The method of claim 1 , further comprising using the first database for cybersecurity.

8 . The method of claim 1 , further comprising using the first database for encrypting or decrypting a message.

9 . The method of claim 8 , further comprising selecting a challenge-hashed-response pair from the first database, the challenge-hashed-response pair being a one-time pad.

10 . The method of claim 1 , further comprising maintaining the first database as a publicly accessible database.

11 . A method, comprising:

receiving a first response bit string associated with a first physically unclonable function (PUF) and an index, wherein the first response bit string corresponds to the index;

querying, using the index, a database to obtain a challenge bit string and a hashed-response bit string, the challenge bit string and the hashed-response bit string corresponding to the index;

inputting the challenge bit string into a second PUF;

capturing a second response bit string from the second PUF;

determining an authentication bit string based on the hashed-response bit string and the second response bit string; and

performing authentication of the first PUF by comparing the first response bit string and the authentication bit string.

12 . The method of claim 11 , wherein the first response bit string and the index are received from a remote device over a network.

13 . The method of claim 11 , further comprising maintaining the database, wherein the database comprises a plurality of challenge-hashed-response pairs, each challenge-hashed-response pair comprising a respective challenge bit string and a respective hashed-response bit string.

14 . The method of claim 11 , wherein the first PUF is authenticated when the authentication bit string is identical to the first response bit string.

15 . The method of claim 11 , wherein the first PUF is not authenticated when the authentication bit string is not identical to the first response bit string.

16 . The method of claim 11 , further comprising using the first PUF to restrict access to one or more databases.

17 . A system comprising:

a physical device;

a first IC chip comprising a first PUF configured to receive a first challenge bit string from the physical device, and generate a first response bit string;

a second IC chip comprising a second PUF configured to receive the first response bit string from the first PUF, receive a second challenge bit string from the physical device, and generate a second response bit string,

wherein:

the physical device is configured to capture the second response bit string from the second PUF, and

perform a hash operation on the first response bit string of the first PUF and the second response bit string of the second PUF, the hash operation generating a hashed-response bit string; and

a database configured to receive and store the first challenge bit string, the second challenge bit string, and the hashed-response bit string.

18 . The system of claim 17 , wherein each of the first PUF and the second PUF comprises a hybrid Boolean network.

19 . The system of claim 17 , wherein the step of performing the hash operation comprises performing an XOR operation on the first response bit string of the first PUF and the second response bit string of the second PUF.

20 . The system of claim 17 , wherein at least one of the first IC chip and the second IC chip is a FPGA or an ASIC.