Decision feedback equalization training for single-ended receiver

1 . A partial equalization decision feedback equalization (DFE) training method, for use with a single-ended receiver, the method, comprising:

obtaining, at a trained strobe position of an equalizing lower-eye (LE), an LE minimum voltage and an LE maximum voltage for a current bit based on a preceding bit, through use of a first comparator and a second comparator;

using the values obtained for the LE minimum voltage and the LE maximum voltage to compute values for an optimal LE reference voltage and an LE DFE tap-coefficient;

obtaining, at a trained strobe position of an equalizing upper-eye (UE), a UE minimum voltage and a UE maximum voltage for the current bit based on the preceding bit, through use of the first comparator and the second comparator;

using the values obtained for the UE minimum voltage and the UE maximum voltage to compute values for an optimal UE reference voltage and a UE DFE tap-coefficient; and

using the values obtained for the LE minimum voltage, the LE maximum voltage, the UE minimum voltage, the UE maximum voltage, the optimal LE reference voltage, and the optimal UE reference voltage to compute final values for the LE DFE tap-coefficient and the UE DFE tap-coefficient.

2 . The partial equalization DFE training method of claim 1 , wherein if the preceding bit is a ‘0’ while in the process of obtaining the LE minimum voltage and the LE maximum voltage, then a first reference voltage representing a minimum value of a [0 to 1] signal transition and a second reference voltage representing a maximum value of a [0 to 0] signal transition are measured and then averaged together to obtain the LE minimum voltage, and wherein if the preceding bit is a ‘1’ while in the process of obtaining the LE minimum voltage and the LE maximum voltage, then a third reference voltage representing a minimum value of a [1 to 1] signal transition and a fourth reference voltage representing a maximum value of a [1 to 0] signal transition are measured and then averaged to obtain the LE maximum voltage.

3 . The partial equalization DFE training method of claim 2 , wherein the process of obtaining the LE minimum voltage and the LE maximum voltage further includes:

setting a reference voltage for the second comparator to be equal to an LE reference voltage threshold, and setting initial values for the LE DFE tap-coefficient and the UE DFE tap-coefficient;

reading bit-values for an incoming data signal;

determining if the preceding bit output from the first comparator is a ‘0’ or a ‘1’ and if the current bit output from the first comparator is a ‘0’ or a ‘1’, such that the nature of the signal transition at the first comparator is ascertained;

determining if the current bit output from the second comparator is a ‘0’ or a ‘1’;

confirming through use of a de-serializer, that a set of values representing the preceding bit output from the first comparator, the current bit output from the first comparator, and the current bit output from the second comparator are either a first set, or a second set;

in response to confirming that the set of values representing the preceding bit output from the first comparator, the current bit output from the first comparator, and the current bit output from the second comparator are either a first set, or a second set, storing the reference voltage for the second comparator as either the first reference voltage or the third reference voltage;

resetting the reference voltage of the second comparator to be equal to an initial value for the LE reference voltage threshold;

reading bit-values for the incoming data signal;

determining if the preceding bit output from the first comparator is a ‘0’ or a ‘1’ and if the current bit output from the first comparator is a ‘0’ or a ‘1’, such that the nature of the signal transition at the first comparator is ascertained;

determining if the current bit output from the second comparator is a ‘0’ or a ‘1’;

confirming through use of the de-serializer, that the set of values representing the preceding bit output from the first comparator, the current bit output from the first comparator, and the current bit output from the second comparator are either a third set, or a fourth set; and

in response to confirming that the set of values representing the preceding bit output from the first comparator, the current bit output from the first comparator, and the current bit output from the second comparator are either a third set, or a fourth set, storing the reference voltage for the second comparator as either the second reference voltage or the fourth reference voltage.

4 . The partial equalization DFE training method of claim 1 , wherein if the preceding bit is a ‘0’ while in the process of obtaining the UE minimum voltage and the UE maximum voltage, then a fifth reference voltage representing a maximum value of a [0 to 0] signal transition and a sixth reference voltage representing a minimum value of a [0 to 1] signal transition are measured and then averaged together to obtain the UE minimum voltage, and wherein if the preceding bit is a ‘1’ while in the process of obtaining the UE minimum voltage and the UE maximum voltage, then a seventh reference voltage representing a maximum value of a [1 to 0] signal transition and a eighth reference voltage representing a minimum value of a [1 to 1] signal transition are measured and then averaged to obtain the UE maximum voltage.

5 . The partial equalization DFE training method of claim 4 , wherein the process of obtaining the UE minimum voltage and the UE maximum voltage further includes:

setting a reference voltage for the first comparator to be equal to a UE reference voltage threshold, and setting initial values for the UE DFE tap-coefficient and the LE DFE tap-coefficient;

reading bit-values for an incoming data signal;

determining if the preceding bit output from the second comparator is a ‘0’ or a ‘1’ and if the current bit output from the second comparator is a ‘0’ or a ‘1’, such that the nature of the signal transition at the second comparator is ascertained;

determining if the current bit output from the first comparator is a ‘0’ or a ‘1’;

confirming through use of a de-serializer, that a set of values representing the preceding bit output from the second comparator, the current bit output from the second comparator, and the current bit output from the first comparator are either a fifth set, or a sixth set;

in response to confirming that the set of values representing the preceding bit output from the second comparator, the current bit output from the second comparator, and the current bit output from the first comparator are either the fifth set, or the sixth set, storing the reference voltage for the first comparator as either the fifth reference voltage or the seventh reference voltage;

resetting the reference voltage for the first comparator to be equal to an initial value for the UE reference voltage threshold;

reading bit-values for the incoming data signal;

determining if the preceding bit output from the second comparator is a ‘0’ or a ‘1’ and if the current bit output from the second comparator is a ‘0’ or a ‘1’, such that the nature of the signal transition at the second comparator is ascertained;

determining if the current bit output from the first comparator is a ‘0’ or a ‘1’;

confirming through use of the de-serializer, that the set of values representing the preceding bit output from the second comparator, the current bit output from the second comparator, and the current bit output from the first comparator are either a seventh set, or an eighth set; and

in response to confirming that the set of values representing the preceding bit output from the second comparator, the current bit output from the second comparator, and the current bit output from the first comparator are either the seventh set, or the eighth set, storing a reference voltage for the second comparator as either the sixth reference voltage or the eighth reference voltage.

6 . The partial equalization DFE training method of claim 1 , wherein the process of computing final values for the LE DFE tap-coefficient and the UE DFE tap-coefficient further includes:

setting a reference voltage for the first comparator to be equal to the optimal LE reference voltage, setting a reference voltage for the second comparator to be equal to the optimal LE reference voltage minus a first offset voltage, and setting the LE DFE tap-coefficient and the UE DFE tap-coefficient to both be equal to a predetermined initial value;

reading bit-values for an incoming data signal;

determining if the preceding bit output from the first comparator is a ‘0’ or a ‘1’ and if the current bit output from the first comparator is a ‘0’ or a ‘1’, such that the nature of the signal transition at the first comparator is ascertained;

determining if the current bit output from the second comparator is a ‘0’ or a ‘1’;

confirming through use of a de-serializer, that a set of values representing the preceding bit output from the first comparator, the current bit output from the first comparator, and the current bit output from the second comparator are equal to a predetermined first set;

in response to confirming that the set of values representing the preceding bit output from the first comparator, the current bit output from the first comparator, and the current bit output from the second comparator are equal to the predetermined first set, storing the reference voltage for the first comparator as the final value for the LE DFE tap-coefficient;

resetting the reference voltage for the second comparator to be equal to the optimal UE reference voltage, resetting a reference voltage for the first comparator to be equal to the optimal UE reference voltage plus a second offset voltage, and resetting the LE DFE tap-coefficient and the UE DFE tap-coefficient to be equal to the predetermined initial value;

reading bit-values for the incoming data signal;

determining if the preceding bit output from the second comparator is a ‘0’ or a ‘1’ and if the current bit output from the second comparator is a ‘0’ or a ‘1’, such that the nature of the signal transition at the second comparator is ascertained;

determining if the current bit output from the first comparator is a ‘0’ or a ‘1’;

confirming through use of the de-serializer, that the set of values representing the preceding bit output from the second comparator, the current bit output from the second comparator, and the current bit output from the first comparator are equal to a predetermined second set; and

in response to confirming that the set of values representing the preceding bit output from the second comparator, the current bit output from the second comparator, and the current bit output from the first comparator are equal to the predetermined second set, storing the reference voltage for the second comparator as the final value for the UE DFE tap-coefficient.

7 . The partial equalization DFE training method of claim 1 , wherein the first comparator is configured to be used as a reference receiver and the second comparator is configured to be used as an error receiver while computing the LE DFE tap-coefficient, and conversely the second comparator is configured to be used as the reference receiver and the first comparator is configured to be used as the error receiver while computing the UE DFE tap-coefficient.

8 . A receiver circuit of a physical layer (PHY) of a memory controller, the receiver circuit comprising:

a data pad configured to receive an input signal from a dynamic random access memory (DRAM) device;

a first comparator operatively connected to the data pad and configured to receive an upper-eye (UE) reference voltage;

a second comparator operatively connected to the data pad and configured to receive a lower-eye (LE) reference voltage; and

a de-serializer operatively connected to both the first comparator and the second comparator, the de-serializer configured to receive a first output from the first comparator, and a second output from the second comparator,

wherein the first comparator is configured to be used as a reference receiver and the second comparator is configured to be used as an error receiver while computing an LE DFE tap-coefficient, and conversely, the second comparator is configured to be used as the reference receiver and the first comparator is configured to be used as the error receiver while computing a UE DFE tap-coefficient.

9 . A full equalization decision feedback equalization (DFE) training method, for use with a receiver, the method, comprising:

obtaining, at a trained strobe position of an equalizing LE (lower-eye), an LE minimum voltage, a mid-level LE voltage, and an LE maximum voltage for a current symbol based on a preceding symbol, through use of a first comparator, a second comparator, and a third comparator;

using the values obtained for the LE minimum voltage, the mid-level LE voltage, and the LE maximum voltage to compute values for an optimal LE reference voltage, a high LE DFE tap-coefficient, and a low LE DFE tap-coefficient;

obtaining, at a trained strobe position of an equalizing UE (upper-eye), a UE minimum voltage, a mid-level UE voltage, and a UE maximum voltage for the current symbol based on the preceding symbol, through use of the first comparator, the second comparator, and the third comparator;

using the values obtained for the UE minimum voltage, the mid-level UE voltage, and the UE maximum voltage to compute values for an optimal UE reference voltage, a high UE DFE tap-coefficient, and a low UE DFE tap-coefficient;

using the values obtained for the LE minimum voltage, the mid-level LE voltage, the LE maximum voltage, and the optimal LE reference voltage to compute final values for the high LE DFE tap-coefficient and the low LE DFE tap-coefficient; and

using the values obtained for the UE minimum voltage, the mid-level UE voltage, the UE maximum voltage, and the optimal UE reference voltage to compute final values for the high UE DFE tap-coefficient and the low UE DFE tap-coefficient.

10 . The full equalization DFE training method of claim 9 , wherein if the preceding symbol is a ‘00’ while in the process of obtaining the LE minimum voltage and the LE maximum voltage, then a first reference voltage representing a minimum value of a [00 to 01] signal transition and a second reference voltage representing a maximum value of a [00 to 00] signal transition are measured and then averaged together to obtain the LE minimum voltage, wherein if the preceding symbol is a ‘01’ while in the process of obtaining the LE minimum voltage and the LE maximum voltage, then a third reference voltage representing a minimum value of a [01 to 01] signal transition and a fourth reference voltage representing a maximum value of a [01 to 00] signal transition are measured and then averaged to obtain a mid-level LE voltage, and wherein if the preceding symbol is a ‘11’ while in the process of obtaining the LE minimum voltage and the LE maximum voltage, then a fifth reference voltage representing a minimum value of a [11 to 01] signal transition and a sixth reference voltage representing a maximum value of a [11 to 00] signal transition are measured and then averaged together to obtain the LE maximum voltage.

11 . The full equalization DFE training method of claim 10 , wherein the process of obtaining the LE minimum voltage, the mid-level LE voltage, and the LE maximum voltage further includes:

setting a reference voltage for the third comparator to be equal to an LE reference voltage threshold, and setting initial values for the high LE DFE tap-coefficient, the low LE DFE tap-coefficient, the high UE DFE tap-coefficient, the low UE DFE tap-coefficient, a low error DFE tap-coefficient, and a high error DFE tap-coefficient;

reading bit-values for an incoming data signal;

determining if a preceding bit output from the first comparator is a ‘0’ or a ‘1’, if a preceding bit output from the second comparator is a ‘0’ or a ‘1’, and if a current bit output from the second comparator is a ‘0’ or a ‘1’, such that the nature of a signal transition of the incoming data signal is ascertained;

determining if the current bit output from the third comparator is a ‘0’ or a ‘1’;

confirming through use of a de-serializer, that a set of values representing the preceding bit output from the first comparator, the preceding bit output from the second comparator, the current bit output from the second comparator, and the current bit output from the third comparator are at least one of a first set, a second set, or a third set;

in response to confirming that the set of values representing the preceding bit output from the first comparator, the preceding bit output from the second comparator, the current bit output from the second comparator, and the current bit output from the third comparator are at least one of the first set, the second set, or the third set, storing the reference voltage for the third comparator voltage as at least one of the second reference voltage, the fourth reference voltage or the sixth reference voltage;

resetting the reference voltage of the third comparator to be equal to an initial value for the LE reference voltage threshold;

reading bit-values for the incoming data signal;

determining if the preceding bit output from the first comparator is a ‘0’ or a ‘1’, if the preceding bit output from the second comparator is a ‘0’ or a ‘1’, and if the current bit output from the second comparator is a ‘0’ or a ‘1’, such that the nature of the signal transition of the incoming data signal is ascertained;

determining if the current bit output from the third comparator is a ‘0’ or a ‘1’;

confirming through use of a de-serializer, that the set of values representing the preceding bit output from the first comparator, the preceding bit output from the second comparator, the current bit output from the second comparator, and the current bit output from the third comparator are at least one of a fourth set, a fifth set or a sixth set; and

in response to confirming that the set of values representing the preceding bit output from the first comparator, the preceding bit output from the second comparator, the current bit output from the second comparator, and the current bit output from the third comparator are at least one of a fourth set, a fifth set, or a sixth set, storing the reference voltage for the third comparator voltage as at least one of the first reference voltage, the third reference voltage or the fifth reference voltage.

12 . The full equalization DFE training method of claim 9 , wherein if the preceding symbol is a ‘00’ while in the process of obtaining the UE minimum voltage and the UE maximum voltage, then a seventh reference voltage representing a minimum value of a [00 to 01] signal transition and an eighth reference voltage representing a minimum value of a [00 to 11] signal transition are measured and then averaged together to obtain the UE minimum voltage, wherein if the preceding symbol is a ‘01’ while in the process of obtaining the UE minimum voltage and the UE maximum voltage, then a ninth reference voltage representing a maximum value of a [01 to 01] signal transition and a tenth reference voltage representing a minimum value of a [01 to 11] signal transition are measured and then averaged to obtain a mid-level UE voltage, and wherein if the preceding symbol is a ‘11’ while in the process of obtaining the UE minimum voltage and the UE maximum voltage, then an eleventh reference voltage representing a maximum value of a [11 to 01] signal transition and a twelfth reference voltage representing a minimum value of a [11 to 11] signal transition are measured and then averaged together to obtain the UE maximum voltage.

13 . The full equalization DFE training method of claim 12 , wherein the process of obtaining the UE minimum voltage and the UE maximum voltage further includes:

setting a reference voltage for the third comparator to be equal to an LE reference voltage threshold, and setting initial values for the high LE DFE tap-coefficient, the low LE DFE tap-coefficient, the high UE DFE tap-coefficient, the low UE DFE tap-coefficient, a low error DFE tap-coefficient, and a high error DFE tap-coefficient;

reading bit-values for an incoming data signal;

determining if a preceding bit output from the first comparator is a ‘0’ or a ‘1’, if a preceding bit output from the second comparator is a ‘0’ or a ‘1’, and if a current bit output from the first comparator is a ‘0’ or a ‘1’, such that the nature of a signal transition of the incoming data signal is ascertained;

determining if the current bit output from the third comparator is a ‘0’ or a ‘1’;

confirming through use of a de-serializer, that a set of values representing the preceding bit output from the first comparator, the preceding bit output from the second comparator, the current bit output from the first comparator, and the current bit output from the third comparator are at least one of a seventh set, an eighth set, or a ninth set;

in response to confirming that the set of values representing the preceding bit output from the first comparator, the preceding bit output from the second comparator, the current bit output from the first comparator, and the current bit output from the third comparator are at least one of the seventh set, the eighth set, or the ninth set, storing the reference voltage for the third comparator voltage as at least one of the seventh reference voltage, the ninth reference voltage or the eleventh reference voltage;

resetting the reference voltage of the third comparator to be equal to an initial value for the UE reference voltage threshold;

reading bit-values for the incoming data signal;

determining if the preceding bit output from the first comparator is a ‘0’ or a ‘1’, if the preceding bit output from the second comparator is a ‘0’ or a ‘1’, and if the current bit output from the first comparator is a ‘0’ or a ‘1’, such that the nature of the signal transition of the incoming data signal is ascertained;

determining if the current bit output from the third comparator is a ‘0’ or a ‘1’;

confirming through use of a de-serializer, that the set of values representing the preceding bit output from the first comparator, the preceding bit output from the second comparator, the current bit output from the first comparator, and the current bit output from the third comparator are at least one of a tenth set, an eleventh set, or a twelfth set; and

in response to confirming that the set of values representing the preceding bit output from the first comparator, the preceding bit output from the second comparator, the current bit output from the first comparator, and the current bit output from the third comparator are at least one of a tenth set, an eleventh set, or a twelfth set, storing the reference voltage for the third comparator voltage as at least one of the eighth reference voltage, the tenth reference voltage or the twelfth reference voltage.

14 . The full equalization DFE training method of claim 9 , wherein the process of computing final values for the high LE DFE tap-coefficient, the low LE DFE tap-coefficient, the high UE DFE tap-coefficient, and the low UE DFE tap-coefficient further includes:

setting a reference voltage for the third comparator to be equal to a first function of the optimal LE reference voltage minus a first offset voltage, and setting a shared predetermined initial value for the high LE DFE tap-coefficient, the low LE DFE tap-coefficient, the high UE DFE tap-coefficient, the low UE DFE tap-coefficient, a high error DFE tap-coefficient, and a low error DFE tap-coefficient;

reading bit-values for an incoming data signal;

determining if a preceding bit output from the first comparator is a ‘0’ or a ‘1’, if a preceding bit output from the second comparator is a ‘0’ or a ‘1’, and if a current bit output from the second comparator is a ‘0’ or a ‘1’, such that the nature of a signal transition of the incoming data signal is ascertained;

determining if the current bit output from the third comparator is a ‘0’ or a ‘1’;

confirming through use of a de-serializer, that a set of values representing the preceding bit output from the first comparator, the preceding bit output from the second comparator, the current bit output from the second comparator, and the current bit output from the third comparator are equal to a predetermined first set;

in response to confirming that the set of values representing the preceding bit output from the first comparator, the preceding bit output from the second comparator, the current bit output from the second comparator, and the current bit output from the third comparator are equal to a predetermined first set, storing the low error DFE tap-coefficient as the low LE DFE tap-coefficient;

setting the reference voltage for the third comparator to be equal to a second function of the optimal LE reference voltage plus a second offset voltage, and resetting the low error DFE tap-coefficient back to the predetermined initial value;

reading bit-values for the incoming data signal;

determining if a preceding bit output from the first comparator is a ‘0’ or a ‘1’, if a preceding bit output from the second comparator is a ‘0’ or a ‘1’, and if a current bit output from the second comparator is a ‘0’ or a ‘1’, such that the nature of a signal transition of the incoming data signal is ascertained;

determining if the current bit output from the third comparator is a ‘0’ or a ‘1’;

confirming through use of a de-serializer, that a set of values representing the preceding bit output from the first comparator, the preceding bit output from the second comparator, the current bit output from the second comparator, and the current bit output from the third comparator are equal to a predetermined second set;

in response to confirming that the set of values representing the preceding bit output from the first comparator, the preceding bit output from the second comparator, the current bit output from the second comparator, and the current bit output from the third comparator are equal to the predetermined second set, storing the high error DFE tap-coefficient as the high LE DFE tap-coefficient;

setting the reference voltage for the third comparator to be equal to a first function of the optimal UE reference voltage minus a third offset voltage, and resetting the high error DFE tap-coefficient back to the predetermined initial value;

reading bit-values for the incoming data signal;

determining if a preceding bit output from the first comparator is a ‘0’ or a ‘1’, if a preceding bit output from the second comparator is a ‘0’ or a ‘1’, and if a current bit output from the first comparator is a ‘0’ or a ‘1’, such that the nature of a signal transition of the incoming data signal is ascertained;

determining if the current bit output from the third comparator is a ‘0’ or a ‘1’;

confirming through use of a de-serializer, that a set of values representing the preceding bit output from the first comparator, the preceding bit output from the second comparator, the current bit output from the first comparator, and the current bit output from the third comparator are equal to the predetermined second set;

in response to confirming that the set of values representing the preceding bit output from the first comparator, the preceding bit output from the second comparator, the current bit output from the first comparator, and the current bit output from the third comparator are equal to the predetermined second set, storing the low error DFE tap-coefficient as the low UE DFE tap-coefficient;

setting the reference voltage for the third comparator to be equal to a second function of the optimal UE reference voltage plus a fourth offset voltage, and resetting the low error DFE tap-coefficient back to the predetermined initial value;

reading bit-values for the incoming data signal;

determining if a preceding bit output from the first comparator is a ‘0’ or a ‘1’, if a preceding bit output from the second comparator is a ‘0’ or a ‘1’, and if a current bit output from the first comparator is a ‘0’ or a ‘1’, such that the nature of a signal transition of the incoming data signal is ascertained;

determining if the current bit output from the third comparator is a ‘0’ or a ‘1’;

confirming through use of a de-serializer, that a set of values representing the preceding bit output from the first comparator, the preceding bit output from the second comparator, the current bit output from the first comparator, and the current bit output from the third comparator are equal to the predetermined second set; and

in response to confirming that the set of values representing the preceding bit output from the first comparator, the preceding bit output from the second comparator, the current bit output from the first comparator, and the current bit output from the third comparator are equal to the predetermined second set, storing the high error DFE tap-coefficient as the high UE DFE tap-coefficient.

15 . The full equalization DFE training method of claim 9 , wherein the first comparator and the second comparator are configured to be used together as a reference receiver and the third comparator is configured to be used as an error receiver.