Using local illumination compensation and delta motion vector refinement together in video coding

Inventors: Yan Zhang (San Diego, CA); Vadim Seregin (San Diego, CA); Hongtao Wang (San Diego, CA); Zhi Zhang (Munich, DE); Chun-Chi Chen (San Diego, CA); Han Huang (San Diego, CA); Marta Karczewicz (San Diego, CA)

Assignee: QUALCOMM Incorporated

H04N19/105 H04N19/109 H04N19/157 H04N19/176 H04N19/44 H04N19/463 H04N19/513 H04N19/573 H04N19/70 H04N19/52

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Quick Facts

Patent No.: US 12676965
App. No.: 18/882,291
Granted: Jul 7, 2026
Kind: B2

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Abstract

Example devices, methods, and computer-readable media are described. An example method includes determining to decode a current block of the video data using a merge mode. The example method includes determining, for the current block, to apply local illumination compensation (LIC). The example method includes determining, for the current block, to apply decoder side motion vector refinement (DMVR). The example method includes decoding the current block based on applying LIC and applying DMVR.

Claims (34)

1 . A method of decoding video data, the method comprising:

determining to decode a current block of the video data using a merge mode;

determining, for the current block, to apply local illumination compensation (LIC);

determining, for the current block, to apply decoder side motion vector refinement (DMVR); and

decoding the current block based on applying LIC and applying DMVR.

2 . The method of claim 1 , further comprising obtaining a LIC flag in a bitstream, wherein determining to apply LIC comprises determining that a value of the LIC flag is equal to 1, and wherein the value of the LIC flag being equal to 1 is indicative of applying LIC.

3 . The method of claim 1 , wherein applying DMVR comprises using mean removed sum of absolute differences (MRSAD).

4 . The method of claim 3 , wherein using MRSAD comprises using MRSAD in lieu of a sum of absolute differences (SAD).

5 . The method of claim 1 , further comprising applying bi-directional optical flow (BDOF) for the current block.

6 . The method of claim 1 , wherein determining to apply DMVR comprises determining that one or more DMVR conditions are met.

7 . The method of claim 1 , wherein the merge mode comprises a regular merge mode, a bilateral matching merge mode, a template matching merge mode, an advanced motion vector predictor merge mode, or an affine merge mode.

8 . The method of claim 7 , wherein the merge mode comprises the affine merge mode, and wherein applying DMVR comprises only applying subblock offset-based affine DMVR refinement.

9 . The method of claim 7 , wherein the merge mode comprises the affine merge mode, and wherein applying DMVR comprises applying subblock offset-based affine DMVR refinement and regression-based affine DMVR refinement.

10 . The method of claim 7 , wherein the merge mode comprises the affine merge mode, and wherein applying DMVR comprises applying affine DMVR and bypassing affine model parameter refinement.

11 . A device for decoding video data, the device comprising:

one or more memories for storing the video data; and

one or more processors implemented in circuitry and communicatively coupled to the one or more memories, the one or more processors configured to:

determine to decode a current block of the video data using a merge mode;

determine, for the current block, to apply local illumination compensation (LIC);

determine, for the current block, to apply decoder side motion vector refinement (DMVR); and

decode the current block based on applying LIC and applying DMVR.

12 . The device of claim 11 , wherein the one or more processors are further configured to obtain an LIC flag in a bitstream, wherein as part of determining to apply LIC, the one or more processors are configured to determine that a value of the LIC flag is equal to 1, and wherein the value of the LIC flag being equal to 1 is indicative of applying LIC.

13 . The device of claim 12 , wherein as part of applying DMVR, the one or more processors are configured to use mean removed sum of absolute differences (MRSAD).

14 . The device of claim 13 , wherein using MRSAD comprises using MRSAD in lieu of a sum of absolute differences (SAD).

15 . The device of claim 11 , wherein the one or more processors are further configured to apply bi-directional optical flow (BDOF) for the current block.

16 . The device of claim 11 , wherein as part of determining to apply DMVR, the one or more processors are configured to determine that one or more DMVR conditions are met.

17 . The device of claim 11 , wherein the merge mode comprises a regular merge mode, a bilateral matching merge mode, a template matching merge mode, an advanced motion vector predictor merge mode, or an affine merge mode.

18 . The device of claim 17 , wherein the merge mode comprises the affine merge mode, and wherein as part of applying DMVR, the one or more processors are configured to apply only subblock offset-based affine DMVR refinement.

19 . The device of claim 17 , wherein the merge mode comprises the affine merge mode, and wherein as part of applying DMVR, the one or more processors are configured to apply subblock offset-based affine DMVR refinement and regression-based affine DMVR refinement.

20 . One or more non-transitory Non transitory computer-readable storage media storing instructions, which when executed, cause one or more processors to:

determine to decode a current block of video data using a merge mode;

determine, for the current block, to apply local illumination compensation (LIC);

determine, for the current block, to apply decoder side motion vector refinement (DMVR); and

decode the current block based on applying LIC and applying DMVR.