Solid-state imaging element, imaging device, and method for controlling solid-state imaging element with a sample-and-hold circuit including a plurality of capacitor elements
A circuit scale is reduced in a solid-state imaging element that combines a plurality of frames. A pre-stage circuit generates an analog signal as a pixel signal. A sample-and-hold circuit holds a high gain signal obtained by amplifying the pixel signal with a gain corresponding to a capacitance of any of a plurality of capacitor elements, and generates a low gain signal obtained by amplifying the pixel signal with a gain corresponding to a ratio of a combined capacitance of the plurality of capacitor elements to the capacitance. A post-stage circuit sequentially reads and outputs the high gain signal and the low gain signal from the sample-and-hold circuit.
1 . A solid-state imaging element comprising:
a pre-stage circuit that generates an analog signal as a pixel signal;
a sample-and-hold circuit that holds a high gain signal obtained by amplifying the pixel signal with a predetermined high gain in any of a plurality of capacitor elements, and generates a low gain signal obtained by amplifying the pixel signal with a low gain that is smaller than the predetermined high gain and corresponds to a combined capacitance of the plurality of capacitor elements; and
a post-stage circuit that sequentially reads and outputs the high gain signal and the low gain signal from the sample-and-hold circuit.
2 . The solid-state imaging element according to claim 1 , wherein
the plurality of capacitor elements includes a first capacitor element, a second capacitor element, a third capacitor element, and a fourth capacitor element, and
the sample-and-hold circuit includes:
the first capacitor element;
the second capacitor element;
the third capacitor element;
the fourth capacitor element; and
a selection circuit that connects one or more of the first capacitor element, the second capacitor element, the third capacitor element, and the fourth capacitor element to the post-stage circuit.
3 . The solid-state imaging element according to claim 2 , wherein
the pre-stage circuit, the sample-and-hold circuit, and the post-stage circuit are disposed in each of a plurality of pixels,
a level of the pixel signal includes a reset level when a floating diffusion layer in the pre-stage circuit is initialized and a signal level when a charge is transferred to the floating diffusion layer,
the pre-stage circuit generates the reset level immediately before a timing at which exposure of all of the plurality of pixels ends, and generates the signal level at the timing, and
the selection circuit connects the first capacitor element to the post-stage circuit immediately before the timing, and connects the third capacitor element to the post-stage circuit at the timing.
4 . The solid-state imaging element according to claim 3 , wherein
the selection circuit sequentially performs control to connect the first capacitor element to the post-stage circuit, control to connect the first capacitor element and the second capacitor element to the post-stage circuit, control to connect the third capacitor element to the post-stage circuit, and control to connect the third capacitor element and the fourth capacitor element to the post-stage circuit within a read period of the pixel signal.
5 . The solid-state imaging element according to claim 3 , wherein
the selection circuit sequentially performs control to connect the first capacitor element to the post-stage circuit, control to connect the first capacitor element and the second capacitor element to the post-stage circuit, and control to connect the third capacitor element to the post-stage circuit in a case where it is determined that the signal level does not exceed a predetermined determination value and to connect the third capacitor element and the fourth capacitor element to the post-stage circuit in a case where it is determined that the signal level is higher than the predetermined determination value within a read period of the pixel signal.
6 . The solid-state imaging element according to claim 5 , further comprising
a determination circuit that determines whether or not the signal level is higher than the predetermined determination value and supplies a determination result to the sample-and-hold circuit.
7 . The solid-state imaging element according to claim 6 , wherein
the determination circuit is disposed in each of the plurality of pixels.
8 . The solid-state imaging element according to claim 6 , wherein
the determination circuit is disposed outside the plurality of pixels.
9 . The solid-state imaging element according to claim 8 , wherein
the determination circuit compares a determination signal corresponding to the predetermined determination value with the high gain signal corresponding to the signal level to generate the determination result.
10 . The solid-state imaging element according to claim 8 , further comprising:
an analog-to-digital converter that converts each of the high gain signal and the low gain signal into a digital signal on a basis of a predetermined ramp signal,
wherein the determination circuit compares the predetermined ramp signal with the high gain signal corresponding to the signal level to generate the determination result.
11 . The solid-state imaging element according to claim 1 , further comprising:
a coupling circuit, wherein
the pre-stage circuit, the sample-and-hold circuit, and the post-stage circuit are disposed in each of a plurality of pixels, and
the coupling circuit couples the sample-and-hold circuit of each of a pair of pixels among the plurality of pixels.
12 . The solid-state imaging element according to claim 11 , wherein
the coupling circuit selects and connects one of the sample-and-hold circuit of each of a pair of pixels arranged in a predetermined direction and the sample-and-hold circuit of each of a pair of pixels arranged in a direction perpendicular to the predetermined direction.
13 . The solid-state imaging element according to claim 1 , further comprising:
a logic circuit that combines a frame in which digital signals obtained by converting high gain signals are arranged and a frame in which digital signals obtained by converting low gain signals are arranged.
14 . The solid-state imaging element according to claim 1 , further comprising:
a post-stage reset transistor that initializes a predetermined post-stage node when the plurality of capacitor elements is disconnected from the predetermined post-stage node, wherein
the plurality of capacitor elements includes a first capacitor element, a second capacitor element, a third capacitor element, and a fourth capacitor element,
the post-stage circuit reads the pixel signal via the predetermined post-stage node, and
the sample-and-hold circuit includes:
the first capacitor element;
the second capacitor element;
the third capacitor element;
the fourth capacitor element; and
a selection circuit that sequentially performs control to connect the first capacitor element to the predetermined post-stage node, control to disconnect the first capacitor element, the second capacitor element, the third capacitor element, and the fourth capacitor element from the predetermined post-stage node, and control to connect the third capacitor element to the predetermined post-stage node.
15 . An imaging device comprising:
a pre-stage circuit that generates an analog signal as a pixel signal;
a sample-and-hold circuit that holds a high gain signal obtained by amplifying the pixel signal with a predetermined high gain in any of a plurality of capacitor elements, and generates a low gain signal obtained by amplifying the pixel signal with a low gain that is smaller than the predetermined high gain and corresponds to a combined capacitance of the plurality of capacitor elements;
a post-stage circuit that sequentially reads and outputs the high gain signal and the low gain signal from the sample-and-hold circuit; and
a recording unit that records a frame generated from the high gain signal and the low gain signal.
16 . A method for controlling solid-state imaging element, the method comprising:
a pre-stage procedure in which a pre-stage circuit generates an analog signal as a pixel signal;
a sample-and-hold procedure in which a sample-and-hold circuit holds a high gain signal obtained by amplifying the pixel signal with a predetermined high gain in any of a plurality of capacitor elements, and generates a low gain signal obtained by amplifying the pixel signal with a low gain that is smaller than the predetermined high gain and corresponds to a combined capacitance of the plurality of capacitor elements; and
a post-stage procedure in which a post-stage circuit sequentially reads and outputs the high gain signal and the low gain signal from the sample-and-hold circuit.