Pulse width modulation signal generation circuit and lamp control system including the same

1 . A pulse width modulation signal generation circuit comprising:

a charging control circuit connected to and located between a first node connected to a capacitor and a voltage line configured to supply an operating voltage, wherein the charging control circuit is configured to control a charging operation for the capacitor in response to an activated charging control signal;

a discharging control circuit connected to and located between the first node and ground, wherein the discharging control circuit is configured to control a discharging operation for the capacitor in response to an activated discharging control signal;

a comparison circuit configured to generate a comparison signal by comparing a first reference voltage and a second reference voltage with a voltage of the first node;

an amplifier configured to generate an enable signal by amplifying a difference between a third reference voltage applied to an inverting terminal and a voltage applied to a non-inverting terminal;

a current supply circuit connected to an output terminal of the amplifier, wherein the current supply circuit is configured to feed back a third current to the non-inverting terminal in response to the enable signal; and

a control logic circuit configured to generate a pulse width modulation signal whose level changes based on a level change of the comparison signal and determine a level change timing for activation of the charging control signal and the discharging control signal using the level change of the comparison signal.

2 . The pulse width modulation signal generation circuit of claim 1 , wherein the comparison circuit includes:

a first comparison circuit configured to compare the first reference voltage with the voltage of the first node to generate a first comparison signal; and

a second comparison circuit configured to compare the second reference voltage with the voltage of the first node to generate a second comparison signal, and

wherein the control logic circuit is configured to change the level of the pulse width modulation signal whenever a level of one of the first comparison signal and the second comparison signal changes.

3 . The pulse width modulation signal generation circuit of claim 1 , wherein the charging control circuit is configured to control the charging operation for the capacitor in response to a bias voltage and the activated charging control signal, and includes;

a current generation circuit configured to generate a first current in response to the bias voltage; and

a charging switch configured to supply the first current to the capacitor in response to the activated charging control signal such that the capacitor is charged with the first current, and

wherein the discharging control circuit is configured to control the discharging operation for the capacitor in response to the enable signal and the activated discharging control signal, and includes:

a current source configured to generate a second current in response to the enable signal;

a current mirror configured to mirror the second current to a mirror branch; and

a discharging switch configured to connect the first node with the mirror branch in response to the activated discharging control signal.

4 . The pulse width modulation signal generation circuit of claim 1 ,

wherein the third current fed back to the non-inverting terminal is adjusted by a resistor connected to and located between the non-inverting terminal and the ground, and

wherein a current amount of a second current and a current amount of the third current are equal to each other.

5 . The pulse width modulation signal generation circuit of claim 1 , further comprising:

a third resistor connected to and located between the non-inverting terminal and the ground,

wherein the third current is adjusted by a resistance circuit connected to the inverting terminal,

wherein the resistance circuit includes:

a first resistor connected to and located between the voltage line and the inverting terminal; and

a second resistor connected to and located between the inverting terminal and the ground,

wherein a voltage applied to the inverting terminal is determined based on voltage distribution of the operating voltage by the first resistor and the second resistor, and the voltage applied to the non-inverting terminal is determined as the third current is applied to the third resistor, and

wherein a current amount of a second current and a current amount of the third current are equal to each other.

6 . The pulse width modulation signal generation circuit of claim 1 , wherein the comparison circuit includes:

a selection circuit configured to output one of the first reference voltage and the second reference voltage in response to a selection signal; and

a third comparison circuit configured to generate the comparison signal by comparing the voltage of the first node with an output voltage of the selection circuit,

wherein the control logic circuit is configured to further determine a level of the selection signal using the level change of the comparison signal,

wherein the third comparison circuit is configured to output the comparison signal whose level changes from a first level to a second level when the voltage of the first node becomes greater than the second reference voltage based on the charging operation for the capacitor,

wherein the control logic circuit is configured to generate the selection signal indicating the output of the first reference voltage based on the comparison signal whose level has changed from the first level to the second level, and generate the activated charging control signal and a deactivated discharging control signal to perform the charging operation for the capacitor,

wherein the third comparison circuit is configured to output the comparison signal whose level changes from the second level to the first level when the voltage of the first node becomes greater than the first reference voltage based on the charging operation for the capacitor, and

wherein the control logic circuit is configured to generate the selection signal indicating the output of the second reference voltage based on the comparison signal whose level has changed from the second level to the first level, and output the activated discharging control signal and a deactivated charging control signal to perform the discharging operation for the capacitor.