IP Library › Granted Patent US 12677369
Granted Patent B2
US 12677369 · App. 18/588,905 · Granted Jul 7, 2026

Printed circuit board

Inventors: Sang Ho Jeong (Suwon-si, KR); Jong Eun Park (Suwon-si, KR); Chang Hwa Park (Suwon-si, KR); Hyun Hu Lee (Suwon-si, KR)
Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
H05K1/0306H05K1/115H05K1/182H05K2201/09827
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Quick Facts
Patent No.
US 12677369
App. No.
18/588,905
Granted
Jul 7, 2026
Kind
B2
Abstract

A printed circuit board includes a first insulating layer; a first wiring layer disposed on an upper surface of the first insulating layer; a second insulating layer disposed on the upper surface of the first insulating layer and having a cavity; and a first barrier layer having at least a portion disposed between the first and second insulating layers and in contact with a side surface of at least a portion of the first wiring layer.

Claims (50)

1 . A printed circuit board, comprising:

a first insulating layer;

a first wiring layer disposed on an upper surface of the first insulating layer;

a second insulating layer disposed on the upper surface of the first insulating layer and having a cavity; and

a first barrier layer having at least a portion disposed between the first and second insulating layers and in contact with a side surface of at least a portion of the first wiring layer,

wherein the first barrier layer contacts at least a portion of an uppermost surface or a lowermost surface of the first wiring layer.

2 . The printed circuit board of claim 1 , wherein the first barrier layer includes an alumina film having a thickness less than 0.1 μm.

3 . The printed circuit board of claim 1 , wherein at least a portion of the first barrier layer is disposed on a bottom surface of the cavity.

4 . The printed circuit board of claim 3 , further comprising:

a first component disposed in the cavity and attached to at least a portion of the first barrier layer disposed on the bottom surface of the cavity; and

second and third components disposed on an upper surface of the second insulating layer and connected to the first component.

5 . The printed circuit board of claim 1 , wherein the cavity exposes at least a portion of the upper surface of the first insulating layer.

6 . The printed circuit board of claim 5 , wherein at least a portion of a side surface of the first barrier layer is exposed through the cavity.

7 . The printed circuit board of claim 6 , wherein at least a portion of a side surface of the first barrier layer exposed through the cavity does not have a step difference with a wall surface of the cavity.

8 . The printed circuit board of claim 5 , wherein at least a portion of the first wiring layer is exposed through the cavity.

9 . The printed circuit board of claim 1 , further comprising:

a second wiring layer disposed on a lower surface of the first insulating layer;

a first via layer penetrating through at least a portion of the first insulating layer and connecting at least a portion of the first wiring layer to at least a portion of the second wiring layer;

a third wiring layer embedded in an upper side of the second insulating layer; and

a second via layer penetrating through at least a portion of the second insulating layer and connecting at least a portion of the first wiring layer to at least a portion of the third wiring layer,

wherein the first wiring layer is embedded in an upper side of the first insulating layer.

10 . The printed circuit board of claim 9 , wherein the first barrier layer covers at least a portion of each of a side surface and a lower surface of at least a portion of the first wiring layer, and at least a portion is in contact with a side surface of the first via layer.

11 . The printed circuit board of claim 9 ,

wherein the cavity exposes at least a portion of the upper surface of the first insulating layer, and

wherein at least a portion of the upper surface of the first insulating layer exposed through the cavity has a step difference from an upper surface of a first portion of the first wiring layer.

12 . The printed circuit board of claim 11 ,

wherein a second portion of the first wiring layer is exposed through the cavity, and

wherein the upper surface of the first portion of the first wiring layer has a step difference from an upper surface of at least a portion of the second portion of the first wiring layer.

13 . The printed circuit board of claim 9 , wherein the first wiring layer is embedded from the upper surface of the first insulating layer, and the second wiring layer protrudes from the lower surface of the first insulating layer.

14 . The printed circuit board of claim 1 , further comprising:

a second wiring layer disposed on a lower surface of the first insulating layer;

a first via layer penetrating through at least a portion of the first insulating layer and connecting at least a portion of the first wiring layer to at least a portion of the second wiring layer;

a third wiring layer disposed on an upper surface of the second insulating layer;

a second via layer penetrating through at least a portion of the second insulating layer and connecting at least a portion of the first wiring layer to at least a portion of the third wiring layer;

a third insulating layer disposed on a lower surface of the first insulating layer;

a fourth wiring layer disposed on a lower surface of the third insulating layer;

a third via layer penetrating through at least a portion of the third insulating layer and connecting at least a portion of the second wiring layer to at least a portion of the fourth wiring layer; and

a second barrier layer having at least a portion disposed between the first and third insulating layers and in contact with a side surface of at least a portion of the second wiring layer.

15 . The printed circuit board of claim 14 ,

wherein the first barrier layer covers at least a portion of each of a side surface and an upper surface of at least a portion of the first wiring layer, and at least a portion of the first barrier layer is in contact with a side surface of the second via layer, and

wherein the second barrier layer covers at least a portion of each of a side surface and a lower surface of at least a portion of the second wiring layer, and at least a portion of the second barrier layer is in contact with a side surface of the third via layer.

16 . The printed circuit board of claim 14 , wherein the first wiring layer and the second wiring layer protrude from the upper surface and the lower surface, respectively, of the first insulating layer.

17 . A printed circuit board, comprising:

a first insulating layer;

a wiring layer disposed on an upper surface of the first insulating layer;

a second insulating layer disposed on an upper surface of the first insulating layer and having a cavity; and

a barrier layer having at least a portion disposed between the first and second insulating layers, and having a stepped portion defined by a first leg in contact with at least a portion of a side surface of the first wiring layer and a second leg in contact with at least a portion of an upper surface or a lower surface of the first wiring layer,

wherein an upper surface of the barrier layer and an upper surface of the wiring layer, or a lower surface of the barrier layer and a lower surface of the wiring layer are substantially coplanar with each other.

18 . The printed circuit board of claim 17 , wherein the barrier layer includes an alumina film having a thickness less than 0.1 μm.

19 . The printed circuit board of claim 17 , wherein at least a portion of the barrier layer is disposed on a bottom surface of the cavity.