Memory device and manufacturing method thereof
A method of forming a memory device including providing a base wafer that includes a substrate, an insulation layer over the substrate, a sacrificial layer over the insulation layer, and a plurality of channel layers embedded in the sacrificial layer and the insulation layer, forming a plurality of grooves in the sacrificial layer each exposing a portion of the insulation layer and separating two adjacent rows of the channel layers, filling the plurality of grooves with an insulation material to form a plurality of spacers, removing the sacrificial layer to form a plurality of trenches that expose portions of the insulation layer and a portion of a sidewall of each of the channel layers, and forming a plurality of gate layers in the trenches.
1 . A memory device comprising:
a substrate;
a plurality of channel layers formed over the substrate and forming an array expanding in a first direction and a second direction different from each other, and the first direction and the second direction being parallel to a surface of the substrate;
a plurality of gate dielectric layers each surrounding, and covering an end of, one of the channel layers;
a plurality of gate layers arranged along the first direction, each of the gate layers continuously extending approximately along the second direction and surrounding one column of the channel layers; and
a plurality of spacers arranged along the first direction, each of the spacers extending approximately along the second direction and separating neighboring ones of the gate layers,
wherein, in the first direction, the gate layers are separated by the spacers and formed between the spacers, and surround the channel layers through the gate dielectric layers; and, in the second direction, the gate layers extend without separation by the spacers and surround the channel layers through the gate dielectric layers.
2 . The memory device of claim 1 , further comprising:
a plurality of storage capacitors;
a first lead-out structure arranged over a top surface of each of the channel layers and formed over the gate structure of each of the channel layers;
a second lead-out structure electrically coupled to the gate layer of a corresponding one of the channel layers to form a word line; and
a third lead-out structure forming an interconnect structure electrically coupling the channel layers, the gate layers, and the storage capacitors.
3 . The memory device of claim 2 , wherein:
each of the storage capacitors includes a first electrode, a second electrode, and a dielectric layer between the first electrode and the second electrode, the second electrode being electrically coupled to ground; and
the interconnect structure includes:
a plurality of first lead-out structures each electrically coupling the first electrode of one of the storage capacitors to a corresponding one of the channel layers; and
a plurality of second lead-out structures each electrically coupled to one of the gate layers.
4 . A memory system comprising:
a memory device including:
a substrate;
a plurality of channel layers formed over the substrate and forming an array expanding in a first direction and a second direction different from each other, and the first direction and the second direction being parallel to a surface of the substrate;
a plurality of gate dielectric layers each surrounding, and covering an end of, one of the channel layers;
a plurality of gate layers arranged along the first direction, each of the gate layers continuously extending approximately along the second direction and surrounding one column of the channel layers; and
a plurality of spacers arranged along the first direction, each of the spacers extending approximately along the second direction and separating neighboring ones of the gate layers; and
a memory controller coupled to the memory device and configured to control operation of the memory device,
wherein, in the first direction, the gate layers are separated by the spacers and formed between the spacers, and surround the channel layers through the gate dielectric layers; and, in the second direction, the gate layers extend without separation by the spacers and surround the channel layers through the gate dielectric layers.