Memory device using semiconductor element
Provided is a memory semiconductor device in which a p-type semiconductor region is formed at an n+layer to which a bit line is connected, an n-type semiconductor layer to which a source line is connected is further formed, a first gate insulating layer and a first gate conductor layer to which a word line is connected exist, a second gate insulating layer and a second gate conductor layer to which a plate line is connected are provided, and a distance from the n+layer to the first gate conductor layer is smaller than a distance up to the second gate conductor layer. At the time of an erase operation, the plate line and the source line have a positive electric potential of the same polarity or have a voltage of 0 V.
1 . A memory cell using a semiconductor element, comprising:
a first semiconductor region that extends in a direction perpendicular to a substrate;
a second semiconductor region that surrounds a part of the first semiconductor region and that is connected thereto;
a third semiconductor region that surrounds a part of the second semiconductor region and that is connected thereto;
a first dielectric film that covers a part of an upper surface of the second semiconductor region;
a first gate conductor layer that contacts an upper surface of the first dielectric film;
a second dielectric film that covers a part of a lower surface of the second semiconductor region; and
a second gate conductor layer that contacts the second dielectric film and whose shortest distance from the first semiconductor region is larger than a shortest distance between the first gate conductor layer and the first semiconductor region,
wherein the memory cell is configured such that a source line is connected to the third semiconductor region, a bit line is connected to the first semiconductor region, a word line is connected to the first gate conductor layer, a plate line is connected to the second gate conductor layer, and a voltage is applied to each of the source line, the bit line, the plate line, the word line, and a control line to perform a write operation, an erase operation, and a read operation, and
when the erase operation of the memory cell is performed, the voltage is applied to only either one of the source line and the bit line.
2 . The memory cell using a semiconductor element according to claim 1 ,
wherein when the read operation or the write operation is performed, polarities of the voltages that are applied to the bit line and the word line are same and differ from a polarity of the voltage that is applied to the plate line.
3 . The memory cell using a semiconductor element according to claim 1 ,
wherein when the erase operation is performed, a voltage having a polarity that is same as a polarity of the voltage that is applied to the plate line is applied to either one of the source line and the bit line, or the voltages that are applied to the source line and the bit line are both 0 V.
4 . The memory cell using a semiconductor element according to claim 1 ,
wherein the second dielectric film is thicker than the first dielectric film.
5 . The memory cell using a semiconductor element according to claim 1 ,
wherein majority carriers of the first semiconductor region and the third semiconductor region are same and differ from a majority carrier of the second semiconductor region.
6 . The memory cell using a semiconductor element according to claim 1 ,
wherein a first metal layer is used in place of the first semiconductor region.
7 . The memory cell using a semiconductor element according to claim 6 ,
wherein the first semiconductor region is used around the first metal layer.
8 . The memory cell using a semiconductor element according to claim 1 , further comprising:
a first metal layer that is connected to an inner portion of the first semiconductor region.
9 . The memory cell using a semiconductor element according to claim 1 ,
wherein an outer periphery of the third semiconductor region is covered by a metal layer.
10 . A memory device using a semiconductor element, comprising:
a plurality of memory cells, each being the memory cell according to claim 1 , that are laid out in a plane,
wherein the second semiconductor region, the third semiconductor region, the first dielectric film, the first gate conductor layer, the second dielectric film, and the second gate conductor layer are shared by the plurality of memory cells that are adjacent to each other in a horizontal direction; other than the first semiconductor region, the memory cells are isolated by a first insulating layer in a perpendicular direction; the first semiconductor region is shared by the memory cells in the perpendicular direction; and the plurality of memory cells are laminated in the perpendicular direction.
11 . A memory device using a semiconductor element,
wherein the memory cells according to claim 10 are disposed by being isolated by a second insulating layer in the horizontal direction.
12 . The memory device using a semiconductor element according to claim 10 ,
wherein the second gate conductor layer is shared by the memory cells that are adjacent to each other in the perpendicular direction.