Memory, storage apparatus, and electronic device

1 . A memory, wherein the memory comprises:

a storage circuit, comprising:

a first bank;

a second bank;

a first global data amplifier, wherein the first bank and the second bank share the first global data amplifier;

first middle input/output (MIO) routing, configured to connect the first bank, the second bank, and the first global data amplifier, wherein the first bank and the second bank share the first MIO;

global input/output (GIO) routing; and

an interface circuit, wherein the first global data amplifier is coupled to the interface circuit through the GIO routing.

2 . The memory according to claim 1 , wherein the storage circuit further comprises a first column decoder shared by the first bank and the second bank.

3 . The memory according to claim 1 , wherein the storage circuit further comprises:

a first column decoder corresponding to the first bank; and

a second column decoder corresponding to the second bank, wherein the first column decoder and the second column decoder share at least one of the following: a decoding power supply circuit or decoding input/output interface routing.

4 . The memory according to claim 1 , wherein the storage circuit further comprises:

a first row decoder;

a third bank; and

a fourth bank, wherein the first bank, the second bank, the third bank, and the fourth bank share the first row decoder.

5 . The memory according to claim 4 , wherein the storage circuit further comprises:

a second global data amplifier, wherein the third bank and the fourth bank share the second global data amplifier.

6 . The memory according to claim 5 , wherein the storage circuit further comprises:

a second MIO configured to connect the third bank, the fourth bank, and the second global data amplifier, wherein the third bank and the fourth bank share the second MIO.

7 . The memory according to claim 4 , wherein the third bank and the fourth bank share the first global data amplifier.

8 . The memory according to claim 7 , wherein the third bank and the fourth bank share the first MIO, and the first MIO is further configured to connect the third bank and the fourth bank.

9 . The memory according to claim 4 , wherein the storage circuit further comprises a third column decoder shared by the third bank and the fourth bank.

10 . The memory according to claim 1 , wherein the storage circuit further comprises:

a selection circuit, configured to select a bank from the first bank and the second bank to connect to the first global data amplifier.

11 . The memory according to claim 10 , wherein each of the first bank and the second bank comprises at least one section, and the selection circuit is further configured to:

select the at least one section of one of the first bank or the second bank to connect to the first global data amplifier.

12 . The memory according to claim 11 , wherein the at least one section comprises a plurality of memory arrays, and the selection circuit is further configured to:

select one of the plurality of memory arrays to connect to the first global data amplifier.

13 . The memory according to claim 1 , wherein the interface circuit comprises:

a first interface circuit configured to: input or output data, and convert the data; and

a second interface circuit configured to: input or output a command, and decode or convert the command.

14 . The memory according to claim 1 , wherein the storage circuit further comprises at least one of the following circuits that are coupled to the GIO routing: a power supply circuit or a test circuit.

15 . A storage apparatus, wherein the storage apparatus comprises:

a controller; and

a memory, wherein the controller is configured to control read/write of the memory, and wherein the memory comprises:

a storage circuit, comprising:

a first bank;

a second bank;

a first global data amplifier, wherein the first bank and the second bank share the first global data amplifier;

first middle input/output (MIO) routing, configured to connect the first bank, the second bank, and the first global data amplifier, wherein the first bank and the second bank share the first MIO;

global input/output (GIO) routing; and

an interface circuit, wherein the first global data amplifier is coupled to the interface circuit through the GIO routing.

16 . The storage apparatus according to claim 15 , wherein the storage circuit further comprises:

a first column decoder shared by the first bank and the second bank.

17 . The storage apparatus according to claim 15 , wherein the storage circuit further comprises:

a first column decoder corresponding to the first bank; and

a second column decoder corresponding to the second bank, wherein the first column decoder and the second column decoder share at least one of the following: a decoding power supply circuit or decoding input/output interface routing.

18 . The storage apparatus according to claim 15 , wherein the storage circuit further comprises:

a selection circuit, configured to select a bank from the first bank and the second bank to connect to the first global data amplifier.

19 . The storage apparatus according to claim 18 , wherein each of the first bank and the second bank comprises at least one section, and the selection circuit is further configured to:

select the at least one section of one of the first bank or the second bank to connect to the first global data amplifier.

20 . The storage apparatus according to claim 19 , wherein the at least one section comprises a plurality of memory arrays, and the selection circuit is further configured to:

select one of the plurality of memory arrays to connect to the first global data amplifier.