One-time programmable (OTP) semiconductor device
A method for fabricating a semiconductor device includes the steps of first providing a substrate comprising an one time programmable (OTP) device region, forming a shallow trench isolation (STI) in the substrate, removing part of the STI to form a first step on a corner of the substrate, forming a first gate oxide layer on the substrate, removing the first gate oxide layer to form a second step on the corner of the substrate, forming a second gate oxide layer on the substrate, and then forming a first gate structure on the substrate and the STI.
1 . A semiconductor device, comprising:
a substrate comprising a one time programmable (OTP) device region;
a shallow trench isolation (STI) in the substrate;
a first gate structure on the STI, wherein the first gate structure comprises a first gate oxide layer on the substrate; and
a first step and a second step between the substrate and the first gate oxide layer and directly under the first gate structure, wherein both the first step and the second step are directly under the first gate oxide layer and higher than a top surface of the STI.
2 . The semiconductor device of claim 1 , wherein the substrate comprises an input/output (I/O) region, the OTP device region, and a core region, the semiconductor device further comprising:
the first gate structure on the OTP device region; and
a second gate structure on the I/O region.
3 . The semiconductor device of claim 2 , wherein the first gate structure comprises:
the first gate oxide layer on the substrate of the OTP device region;
a first high-k dielectric layer on first gate oxide layer;
a first work function metal (WFM) layer on the first high-k dielectric layer; and
a first low resistance metal layer on the first WFM layer.
4 . The semiconductor device of claim 3 , wherein the second gate structure comprises:
a second gate oxide layer on the substrate of the I/O region;
a second high-k dielectric layer on the second gate oxide layer;
a second work function metal (WFM) layer on the second high-k dielectric layer; and
a second low resistance metal layer on the second WFM layer.
5 . The semiconductor device of claim 4 , wherein a bottom surface of the first high-k dielectric layer is lower than a bottom surface of the second high-k dielectric layer.
6 . The semiconductor device of claim 4 , wherein a top surface of the first high-k dielectric layer is even with a top surface of the second high-k dielectric layer.
7 . The semiconductor device of claim 3 , wherein the first high-k dielectric layer comprises a third step and a fourth step on the substrate adjacent to the STI.
8 . The semiconductor device of claim 3 , wherein the first gate oxide layer comprises a fifth step and a sixth step on the substrate adjacent to the STI.