Three-dimensional memory device including horizontal semiconductor channels and methods of forming the same
A method of forming three-dimensional memory device includes forming an alternating stack of insulating layers and semiconductor material layers over a substrate, and forming laterally alternating sequences of laterally-insulated electrode structures and dielectric isolation pillar structures through the alternating stack. At least a portion of the laterally-insulated electrode structures each include a memory film and a word line electrode.
1 . A semiconductor device, comprising:
a vertically alternating sequence of vertically-perforated insulating layers and vertically-perforated composite layers, wherein a plurality of elongated openings vertically extends through each of the vertically-perforated insulating layers and the vertically-perforated composite layers in the vertically alternating sequence; each of the vertically-perforated composite layers comprises a respective plurality of horizontal semiconductor channel strips; and each of the respective plurality of horizontal semiconductor channel strips is located between each neighboring pair of the plurality of elongated openings; and
laterally alternating sequences of laterally-insulated electrode structures and dielectric isolation pillar structures, wherein each of the laterally alternating sequences is located within a respective elongated opening of the plurality of elongated openings; and a respective subset of the laterally-insulated electrode structures and a respective subset of the dielectric isolation pillar structures laterally alternate along a first horizontal direction within each of the laterally alternating sequences;
wherein each of the vertically-perforated composite layers further comprises:
a respective source region contacting a first end of each horizontal semiconductor channel strip of the respective plurality of horizontal semiconductor channel strips; and
a respective plurality of drain regions contacting a second end of a respective one of the respective plurality of the horizontal semiconductor channel strips;
wherein:
the respective source region forms a first p-n junction with the first end of each horizontal semiconductor channel strip of the respective plurality of horizontal semiconductor channel strips;
the respective plurality of drain regions form second p-n junctions with the second ends of the respective one of the respective plurality of the horizontal semiconductor channel strips;
the respective source region contacts each horizontal semiconductor channel strip of the respective plurality of horizontal semiconductor channel strips; and
the respective plurality of drain regions are laterally spaced apart from each other by the laterally alternating sequences of laterally-insulated electrode structures and dielectric isolation pillar structures.
2 . A semiconductor device, comprising:
a vertically alternating sequence of vertically-perforated insulating layers and vertically-perforated composite layers, wherein a plurality of elongated openings vertically extends through each of the vertically-perforated insulating layers and the vertically-perforated composite layers in the vertically alternating sequence; each of the vertically-perforated composite layers comprises a respective plurality of horizontal semiconductor channel strips; and each of the respective plurality of horizontal semiconductor channel strips is located between each neighboring pair of the plurality of elongated openings; and
laterally alternating sequences of laterally-insulated electrode structures and dielectric isolation pillar structures, wherein each of the laterally alternating sequences is located within a respective elongated opening of the plurality of elongated openings; and a respective subset of the laterally-insulated electrode structures and a respective subset of the dielectric isolation pillar structures laterally alternate along a first horizontal direction within each of the laterally alternating sequences;
wherein each of the vertically-perforated composite layers further comprises:
a respective source region contacting a first end of each horizontal semiconductor channel strip of the respective plurality of horizontal semiconductor channel strips; and
a respective plurality of drain regions contacting a second end of a respective one of the respective plurality of the horizontal semiconductor channel strips;
further comprising a source line extending through each layer within the vertically alternating sequence and comprising:
a doped semiconductor spacer comprising vertically-extending wall portions and contacting each of the source regions of the vertically-perforated composite layers; and
an electrically conductive core contacting inner sidewalls of the doped semiconductor spacer.
3 . A semiconductor device, comprising:
a vertically alternating sequence of vertically-perforated insulating layers and vertically-perforated composite layers, wherein a plurality of elongated openings vertically extends through each of the vertically-perforated insulating layers and the vertically-perforated composite layers in the vertically alternating sequence; each of the vertically-perforated composite layers comprises a respective plurality of horizontal semiconductor channel strips; and each of the respective plurality of horizontal semiconductor channel strips is located between each neighboring pair of the plurality of elongated openings; and
laterally alternating sequences of laterally-insulated electrode structures and dielectric isolation pillar structures, wherein each of the laterally alternating sequences is located within a respective elongated opening of the plurality of elongated openings; and a respective subset of the laterally-insulated electrode structures and a respective subset of the dielectric isolation pillar structures laterally alternate along a first horizontal direction within each of the laterally alternating sequences;
wherein a first subset of the laterally-insulated electrode structures comprises memory pillar structures each including a memory film and a word line electrode.
4 . The semiconductor device of claim 3 , wherein the memory film comprises, from outside to inside, a tunneling dielectric layer, a memory material layer, and a blocking dielectric layer.
5 . The semiconductor device of claim 3 , wherein a second subset of the laterally-insulated electrode structures comprises insulated drain-select pillar structures including a layer stack having a same composition as the memory film and further including a drain-select electrode.
6 . A semiconductor device, comprising:
a vertically alternating sequence of vertically-perforated insulating layers and vertically-perforated composite layers, wherein a plurality of elongated openings vertically extends through each of the vertically-perforated insulating layers and the vertically-perforated composite layers in the vertically alternating sequence; each of the vertically-perforated composite layers comprises a respective plurality of horizontal semiconductor channel strips; and each of the respective plurality of horizontal semiconductor channel strips is located between each neighboring pair of the plurality of elongated openings; and
laterally alternating sequences of laterally-insulated electrode structures and dielectric isolation pillar structures, wherein each of the laterally alternating sequences is located within a respective elongated opening of the plurality of elongated openings; and a respective subset of the laterally-insulated electrode structures and a respective subset of the dielectric isolation pillar structures laterally alternate along a first horizontal direction within each of the laterally alternating sequences;
wherein each of the laterally-insulated electrode structures comprises two vertical stacks of outer surface segments contacting surface segments of two vertical stacks of horizontal semiconductor channel strips.
7 . The semiconductor device of claim 6 , wherein:
each outer surface segment within the two vertical stacks of outer surface segments comprises a vertically-straight and laterally convex-surface segment; and
each surface segment of the two vertical stacks of horizontal semiconductor channel strips that contacts a respective laterally-insulated electrode structure comprises a vertically-straight and laterally-concave surface segment.
8 . A semiconductor device, comprising:
a vertically alternating sequence of vertically-perforated insulating layers and vertically-perforated composite layers, wherein a plurality of elongated openings vertically extends through each of the vertically-perforated insulating layers and the vertically-perforated composite layers in the vertically alternating sequence; each of the vertically-perforated composite layers comprises a respective plurality of horizontal semiconductor channel strips; and each of the respective plurality of horizontal semiconductor channel strips is located between each neighboring pair of the plurality of elongated openings; and
laterally alternating sequences of laterally-insulated electrode structures and dielectric isolation pillar structures, wherein each of the laterally alternating sequences is located within a respective elongated opening of the plurality of elongated openings; and a respective subset of the laterally-insulated electrode structures and a respective subset of the dielectric isolation pillar structures laterally alternate along a first horizontal direction within each of the laterally alternating sequences;
wherein one of the dielectric isolation pillar structures comprises:
a pair of vertically-straight and laterally-convex surface segments contacting two vertical stacks of horizontal semiconductor channel strips; and
a pair of vertically-straight and laterally-concave surface segments contacting a neighboring pair of the laterally-insulated electrode structures.
9 . A method of forming three-dimensional memory device, comprising:
forming an alternating stack of insulating layers and semiconductor material layers over a substrate; and
forming laterally alternating sequences of laterally-insulated electrode structures and dielectric isolation pillar structures through the alternating stack, wherein at least a portion of the laterally-insulated electrode structures each comprise a memory film and a word line electrode.
10 . The method of claim 9 , wherein remaining portions of the semiconductor material layers comprise horizontal semiconductor channel strips after the step of forming laterally alternating sequences of laterally-insulated electrode structures and dielectric isolation pillar structures through the alternating stack.
11 . The method of claim 10 , further comprising:
doping first ends of the horizontal semiconductor channel strips to form a common source layer contacting the horizontal semiconductor channel strips; and
doping a second ends of the horizontal semiconductor channel strips to form a plurality of laterally spaced apart drain regions.
12 . The method of claim 11 , further comprising:
forming horizontal bit lines in contact with the plurality of laterally spaced apart drain regions; and
forming layer contact via structures contacting a top surface of a respective one of the bit lines.
13 . The method of claim 9 , further comprising:
forming isolation openings through the alternating stack;
forming the dielectric isolation pillar structures in the isolation openings;
forming electrode openings through the alternating stack such that electrode openings cut through peripheral portions of the dielectric isolation pillar structures; and
forming the laterally-insulated electrode structures in the electrode openings.