Three dimensional (3D) memory device and fabrication method
A method for fabricating a 3D memory device includes forming a sacrificial layer over a substrate, forming a first dielectric stack over the sacrificial layer, forming a channel hole structure, forming an opening that exposes the sacrificial layer, removing the sacrificial layer to create a cavity and expose a part of the channel hole structure, forming a semiconductor layer to fill the cavity, filling the opening with a filling structure, and forming a second dielectric stack over the filling structure. The opening is made for a gate line slit (GLS) structure.
1 . A three-dimensional ( 3 D) memory device, comprising:
a first conductor/insulator stack including a first conductive layer and a first dielectric layer alternatingly stacked;
a second conductor/insulator stack formed over and aligned with the first conductor/insulator stack and including a second conductive layer and a second dielectric layer alternatingly stacked;
a channel hole structure including:
a first semiconductor channel extending through the first conductor/insulator stack along a first direction,
a first conductive plug formed on a sidewall surface of an upper portion of the first semiconductor channel, and
a second semiconductor channel formed over the first conductive plug and through the second conductor/insulator stack; and
a gate line slit (GLS) structure, the GLS structure including a first taper part through the first conductor/insulator stack and a second taper part through the second conductor/insulator stack along the first direction.
2 . The 3D memory device according to claim 1 , wherein the first taper part tapers from a first end with a first dimension to a second end with a second dimension along the first direction, the second taper part tapers from a third end with a third dimension to a fourth end with a fourth dimension along the first direction, the first end of the first taper part connects with the fourth end of the second taper part, and the first dimension is larger than the fourth dimension, the first, second, third, and fourth dimensions measured along a second direction that is perpendicular to the first direction.
3 . The 3D memory device according to claim 1 , wherein the first taper part tapers from a first end with a first dimension to a second end with a second dimension along the first direction, the second taper part tapers from a third end with a third dimension to a fourth end with a fourth dimension along the first direction, the first end of the first taper part connects with the fourth end of the second taper part, and the first dimension is smaller than the fourth dimension by a predetermined value, the first, second, third, and fourth dimensions measured along a second direction that is perpendicular to the first direction.
4 . The 3D memory device according to claim 1 , wherein the channel hole structure comprises:
a first functional layer through the first conductor/insulator stack and including a first blocking layer, a first charge trap layer, and/or a first tunneling layer,
wherein the first semiconductor channel is formed over the first functional layer; and
a second functional layer through the second conductor/insulator stack and over the first conductive plug,
wherein the second semiconductor channel is formed over the second functional layer, the first and second semiconductor channels connected electrically.
5 . The 3D memory device according to claim 4 , further comprising:
a semiconductor layer, a portion of the semiconductor layer passing through the first functional layer and contacting the first semiconductor channel.
6 . The 3D memory device according to claim 4 , wherein the first conductive plug has a top surface coplanar with a top surface of the upper portion of the first semiconductor channel.
7 . The 3D memory device according to claim 4 , wherein the first conductive plug is in direct contact with the second functional layer.
8 . The 3D memory device according to claim 7 , wherein the fourth dielectric layer extends along the lateral direction to connect with each of the first and second dielectric layers.
9 . The 3D memory device according to claim 7 , wherein the SCT further includes a dielectric structure and a conductive structure surrounding the dielectric structure and the conductive structure is in contact with the third conductive layer, and/or the dielectric structure includes a dielectric layer enclosing an air gap there-in.
10 . The 3D memory device according to claim 7 , wherein an orthographic projection of the third conductive layer in each third dielectric layer in the dielectric stack on a plane along the lateral direction are non-overlapped.
11 . The 3D memory device according to claim 7 , wherein when one or more of the third and fourth dielectric layers are formed between one third conductive layer in the dielectric stack and a corresponding contact via, the SCT passes through the one or more of the third and fourth dielectric layers to connect to the corresponding contact via.
12 . The 3D memory device according to claim 7 , wherein one third conductive layer is formed in one third dielectric layer and corresponds to one of the first and second conductive layers.
13 . The 3D memory device according to claim 1 , further comprising:
a third conductor/insulator stack formed over and aligned with the second conductor/insulator stack and including a third conductive layer and a third dielectric layer alternatingly stacked, the channel hole structure extending through the first, second, and third conductor/insulator stacks, and the GLS structure further including a third taper part through the third conductor/insulator stack.
14 . The 3D memory device according to claim 1 , further comprising:
a third conductor/insulator stack formed over and aligned with the second conductor/insulator stack and including a third conductive layer and a third dielectric layer alternatingly stacked, the channel hole structure extending through the first, second, and third conductor/insulator stacks, and the second taper part extends through the second and third conductor/insulator stacks.
15 . The 3D memory device according to claim 1 , wherein the channel hole structure comprises a first dielectric layer formed on a sidewall surface of a lower portion of the first semiconductor channel and under the first conductive plug.
16 . The 3D memory device according to claim 1 , further comprising:
a dielectric stack including a third dielectric layer and a fourth dielectric layer alternatingly stacked, wherein the third dielectric layer extends along a lateral direction to connect with each of the first and second conductive layers;
a third conductive layer formed in and through the third dielectric layer in the dielectric stack; and
a staircase contact (SCT) formed on the third conductive layer and extending along a vertical direction to connect to a contact via formed over the dielectric stack.
17 . A system, comprising:
a memory device; and
a memory controller for controlling the memory device, the memory device comprising:
a first conductor/insulator stack including a first conductive layer and a first dielectric layer alternatingly stacked;
a second conductor/insulator stack formed over and aligned with the first conductor/insulator stack and including a second conductive layer and a second dielectric layer alternatingly stacked;
a channel hole structure including:
a first semiconductor channel extending through the first conductor/insulator stack along a first direction,
a first conductive plug formed on a sidewall surface of an upper portion of the first semiconductor channel, and
a second semiconductor channel formed over the first conductive plug and through the second conductor/insulator stack; and
a gate line slit (GLS) structure, the GLS structure including a first taper part through the first conductor/insulator stack and a second taper part through the second conductor/insulator stack along the first direction.
18 . The system according to claim 17 , wherein the first taper part tapers from a first end with a first dimension to a second end with a second dimension along the first direction, the second taper part tapers from a third end with a third dimension to a fourth end with a fourth dimension along the first direction, the first end of the first taper part connects with the fourth end of the second taper part, and the first dimension is larger than the fourth dimension, the first, second, third, and fourth dimensions measured along a second direction that is perpendicular to the first direction.
19 . The system according to claim 17 , wherein the first taper part tapers from a first end with a first dimension to a second end with a second dimension along the first direction, the second taper part tapers from a third end with a third dimension to a fourth end with a fourth dimension along the first direction, the first end of the first taper part connects with the fourth end of the second taper part, and the first dimension is smaller than the fourth dimension by a predetermined value, the first, second, third, and fourth dimensions measured along a second direction that is perpendicular to the first direction.
20 . The system according to claim 17 , wherein the memory device further comprises:
a third conductor/insulator stack formed over and aligned with the second conductor/insulator stack and including a third conductive layer and a third dielectric layer alternatingly stacked, the channel hole structure extending through the first, second, and third conductor/insulator stacks, and the GLS structure further including a third taper part through the third conductor/insulator stack.