Single crystal silicon cores for stacked memory cells
Methods, systems, and devices for single crystal silicon cores for stacked memory cells are described. A memory device may be formed using silicon cores that are each associated with a set of multiple memory cells. Multiple silicon cores may extend along a first direction, and multiple sleeves of memory materials and conductive materials may be formed around each silicon core. Each sleeve of memory materials may be associated with a respective memory cell and each conductive material may be associated with a word line, such that each silicon core may be associated with multiple memory cells. The respective sleeves of memory materials and conductive materials may be formed from larger sleeves of material that may be etched into sections of the memory materials and the conductive materials along the silicon cores.
1 . An apparatus, comprising:
a plurality of silicon cores that each extend along a first direction and are each associated with a respective plurality of memory cells, wherein the plurality of silicon cores comprises respective subsets of aligned silicon cores each located at a different level along a third direction;
a plurality of memory materials that each surround a respective portion of a corresponding silicon core of the plurality of silicon cores in a second direction, wherein the plurality of memory materials comprises respective subsets of aligned memory materials each located at a different level along the third direction; and
a respective conductive material associated with each respective subset of memory materials, the respective conductive material surrounding the respective subset of memory materials in the second direction.
2 . The apparatus of claim 1 , wherein the respective conductive material is operable to apply a voltage to a respective gate electrode associated with each memory material of a second subset of memory materials corresponding to the respective conductive material.
3 . The apparatus of claim 1 , further comprising:
a respective polysilicon contact coupled with each first subset of silicon cores, the respective polysilicon contacts extending along the second direction; and
a respective conductive line extending along a fourth direction and coupled with multiple silicon cores of the plurality of silicon cores at a same level.
4 . The apparatus of claim 3 , wherein the respective polysilicon contact comprises a highly-doped n-type polysilicon associated with a source contact.
5 . The apparatus of claim 3 , wherein a memory cell of the respective plurality of memory cells is operable to be activated based at least in part on a first voltage applied to the respective conductive material associated with the memory cell and a second voltage applied to the respective conductive line associated with the memory cell.
6 . The apparatus of claim 3 , wherein each of the respective conductive lines comprises:
a respective polysilicon material coupled with the multiple silicon cores;
a respective contact material coupled with the respective polysilicon material; and
a respective second conductive material coupled with the respective contact material.
7 . The apparatus of claim 3 , further comprising:
a respective contact coupled with each conductive line of the respective conductive lines, the respective contacts each operable to apply a respective voltage to the respective conductive line.
8 . The apparatus of claim 1 , wherein each of the memory materials comprises a respective gate material associated with a respective memory cell.