Memory structure including a plurality of transistors connected to a storage element
A memory structure includes a substrate. The memory structure further includes a first transistor, wherein the first transistor is a first distance from the substrate. The memory structure further includes a second transistor, wherein the second transistor is a second distance from the substrate, and the first distance is different from the second distance, and a first source/drain (S/D) region of the first transistor is connected to a second S/D region of the second transistor. The memory structure further includes a plurality of storage elements electrically connected to both the first transistor and the second transistor, wherein each of the plurality of storage elements is a third distance from the substrate, and the third distance is different from both the first distance and the second distance.
1 . A memory structure comprising:
a substrate;
a first transistor, wherein the first transistor is a first distance from the substrate;
a second transistor, wherein the second transistor is a second distance from the substrate, and the first distance is different from the second distance, and a first source/drain (S/D) region of the first transistor is connected to a second S/D region of the second transistor; and
a plurality of storage elements electrically connected to both the first transistor and the second transistor, wherein each of the plurality of storage elements is a third distance from the substrate, and the third distance is different from both the first distance and the second distance.
2 . The memory structure of claim 1 , wherein the first transistor is a write transistor.
3 . The memory structure of claim 2 , wherein the second transistor is a read transistor.
4 . The memory structure of claim 1 , wherein the third distance is between the first distance and the second distance.
5 . The memory structure of claim 1 , wherein the second transistor comprises:
a gate; and
a channel layer, wherein the gate is between the channel layer and the substrate.
6 . The memory structure of claim 1 , further comprising a bit line, wherein the bit line is electrically connected between the first S/D region and the second S/D region.
7 . The memory structure of claim 1 , further comprising a source line, wherein the source line is connected to the second transistor, and the second transistor is between the source line and the substrate.
8 . The memory structure of claim 1 , further comprising a reference voltage carrying conductive line electrically connected to the second transistor, wherein the second transistor is between the reference voltage carrying conductive line and the substrate.
9 . The memory structure of claim 1 , further comprising a bit line, wherein the bit line is selectively electrically connectable to the second transistor.
10 . The memory structure of claim 1 , wherein the second transistor is directly above the first transistor in a plan view.
11 . A semiconductor device comprising:
a substrate;
a write transistor partially in the substrate;
an interconnect structure over the substrate;
a read transistor entirely within the interconnect structure; and
at least one storage element electrically connected to the write transistor and to the read transistor, wherein the write transistor is configured to control each of the at least one storage element, and the read transistor is configured to output a signal based on each of the least one storage element.
12 . The semiconductor device of claim 11 , wherein each of the at least one storage element comprises a ferroelectric random-access memory (FeRAM).
13 . The semiconductor device of claim 11 , wherein each of the at least one storage element comprises a ferroelectric tunneling junction (FTJ).
14 . The semiconductor device of claim 11 , wherein the at least one storage element is physically between the write transistor and the read transistor.
15 . The semiconductor device of claim 11 , further comprising a bit line, wherein the bit line is permanently electrically connected to each of the read transistor and the write transistor.
16 . The semiconductor device of claim 11 , further comprising a bit line, wherein the bit line is selectively electrically connected to the read transistor.
17 . The semiconductor device of claim 11 , wherein the read transistor comprises:
a gate; and
a channel layer, wherein the gate is between the channel layer and the substrate.
18 . A memory structure comprising:
a substrate;
a first transistor, wherein the first transistor comprises a gate structure, a first source/drain (S/D) region, and a second S/D region;
a second transistor, wherein the second transistor has a gate electrode, and a gate dielectric, and the gate electrode is physically between the gate structure and the gate dielectric; and
a storage element electrically connected to the first S/D region, wherein the storage element is physically between the first transistor and the second transistor.
19 . The memory structure of claim 18 , wherein the storage element is electrically connected to the gate electrode.
20 . The memory structure of claim 18 , wherein the second S/D region is electrically connected to the second transistor.