Three-dimensional ferroelectric memory devices
A three-dimensional ferroelectric memory device includes a channel on a substrate and extending in a vertical direction substantially perpendicular to an upper surface of the substrate, a gate insulation pattern and a conductive pattern stacked on and surrounding a sidewall of the channel in a horizontal direction substantially parallel to the upper surface of the substrate, a ferroelectric pattern contacting a portion of an outer sidewall of the conductive pattern, a gate electrode contacting the ferroelectric pattern, and first and second source/drain patterns contacting lower and upper surfaces, respectively, of the channel.
1 . A three-dimensional ferroelectric memory device, comprising:
a substrate;
a channel on the substrate, the channel extending in a vertical direction substantially perpendicular to an upper surface of the substrate;
a gate insulation pattern and a conductive pattern stacked on and surrounding a sidewall of the channel in a horizontal direction substantially parallel to the upper surface of the substrate;
a ferroelectric pattern contacting a portion of an outer sidewall of the conductive pattern;
a gate electrode contacting the ferroelectric pattern;
a first source/drain pattern contacting a lower surface of the channel; and
a second source/drain pattern contacting an upper surface of the channel.
2 . The three-dimensional ferroelectric memory device as claimed in claim 1 , wherein a length in the vertical direction of the conductive pattern is greater than a length in the vertical direction of the gate electrode.
3 . The three-dimensional ferroelectric memory device as claimed in claim 1 , wherein the channel has a shape of a pillar extending in the vertical direction.
4 . The three-dimensional ferroelectric memory device as claimed in claim 1 , wherein the channel has a shape of a hollow cylinder extending in the vertical direction.
5 . The three-dimensional ferroelectric memory device as claimed in claim 1 , wherein the channel includes:
a first channel having a shape of a cup; and
a second channel having a shape of a cup, the second channel contacting an upper surface of the first channel.
6 . The three-dimensional ferroelectric memory device as claimed in claim 5 , further comprising a filling pattern, a lower surface and a sidewall of the filling pattern being covered by the first channel, and an upper surface of the filling pattern being covered by the second channel.
7 . The three-dimensional ferroelectric memory device as claimed in claim 5 , wherein each of the first channel and the second channel includes a two-dimensional material.
8 . The three-dimensional ferroelectric memory device as claimed in claim 1 , wherein each of the first source/drain pattern and the second source/drain pattern includes polysilicon or silicon-germanium doped with n-type or p-type impurities.
9 . The three-dimensional ferroelectric memory device as claimed in claim 1 , wherein the first source/drain pattern has a shape of a pillar.
10 . The three-dimensional ferroelectric memory device as claimed in claim 1 , wherein the first source/drain pattern has a shape of a line extending in a predetermined direction.
11 . The three-dimensional ferroelectric memory device as claimed in claim 1 , wherein a sidewall of the second source/drain pattern is covered by the gate insulation pattern.
12 . The three-dimensional ferroelectric memory device as claimed in claim 1 , further comprising:
a bit line on the substrate, the bit line extending in a first direction substantially parallel to the upper surface of the substrate and contacting the first source/drain pattern; and
a source line on the second source/drain pattern, the source line extending in the first direction and being connected to the second source/drain pattern.
13 . The three-dimensional ferroelectric memory device as claimed in claim 12 , wherein the gate electrode extends in a second direction substantially parallel to the upper surface of the substrate and crossing the first direction, the gate electrode being a word line.
14 . A three-dimensional ferroelectric memory device, comprising:
a substrate;
a channel on the substrate, the channel extending in a vertical direction substantially perpendicular to an upper surface of the substrate;
a gate insulation pattern and a conductive pattern sequentially stacked on a sidewall of the channel in a horizontal direction substantially parallel to the upper surface of the substrate;
a ferroelectric pattern contacting a portion of an outer sidewall of the conductive pattern;
a gate electrode contacting the ferroelectric pattern;
a first source/drain pattern contacting a lower surface of the channel; and
a second source/drain pattern contacting an upper surface of the channel,
wherein an area of a portion of the gate insulation pattern between and contacting the channel and the conductive pattern is greater than an area of a portion of the ferroelectric pattern between and contacting the conductive pattern and the gate electrode.
15 . The three-dimensional ferroelectric memory device as claimed in claim 14 , wherein a width of the portion of the gate insulation pattern in the horizontal direction is greater than a width of the portion of the ferroelectric pattern in the horizontal direction.
16 . The three-dimensional ferroelectric memory device as claimed in claim 14 , wherein a height of the portion of the gate insulation pattern in the vertical direction is greater than a height of the portion of the ferroelectric pattern in the vertical direction.
17 . A three-dimensional ferroelectric memory device, comprising:
a substrate;
a bit line on the substrate, the bit line extending in a first direction substantially parallel to an upper surface of the substrate;
a first source/drain pattern contacting an upper surface of the bit line;
a channel contacting an upper surface of the first source/drain pattern, the channel extending in a vertical direction substantially perpendicular to the upper surface of the substrate;
a gate insulation pattern and a conductive pattern stacked on and surrounding a sidewall of the channel in a horizontal direction substantially parallel to the upper surface of the substrate;
a ferroelectric pattern contacting a portion of an outer sidewall of the conductive pattern;
a word line contacting the ferroelectric pattern, the word line extending in a second direction substantially parallel to the upper surface of the substrate and crossing the first direction;
a second source/drain pattern contacting an upper surface of the channel; and
a source line contacting an upper surface of the second source/drain pattern, the source line extending in the first direction.
18 . The three-dimensional ferroelectric memory device as claimed in claim 17 , wherein the bit line is one of a plurality of bit lines spaced apart from each other in the second direction, the word line is one of a plurality of word lines spaced apart from each other in the first direction, and the source line is one of a plurality of source lines spaced apart from each other in the second direction.
19 . The three-dimensional ferroelectric memory device as claimed in claim 18 , further comprising an insulation pattern on the plurality of bit lines between ones of the plurality of word lines neighboring in the first direction, a pillar structure including the channel, the gate insulation pattern, and the conductive pattern extending through the insulation pattern.
20 . The three-dimensional ferroelectric memory device as claimed in claim 19 , wherein:
the pillar structure is one of a plurality of pillar structures spaced apart from each other between ones of the word lines neighboring in the first direction, and
the plurality of pillar structures are arranged in a zigzag pattern in the second direction.