Three-dimensional ferroelectric memory device
A three-dimensional (3D) ferroelectric memory device may include a plurality of gate electrodes stacked on a substrate, a plurality of ferroelectric layers in contact with the plurality of gate electrodes, a plurality of intermediate electrodes in contact with the plurality of ferroelectric layers, a gate insulating layer in contact with the plurality of intermediate electrodes, and a channel layer in contact with the gate insulating layer. Widths of the intermediate electrodes may be greater than widths of the ferroelectric layers in contact with the intermediate electrodes.
1 . A three-dimensional (3D) ferroelectric memory device comprising:
a substrate;
a plurality of gate electrodes stacked on the substrate;
a plurality of ferroelectric layers in contact with the plurality of gate electrodes;
a plurality of intermediate electrodes in contact with the plurality of ferroelectric layers;
a gate insulating layer in contact with the plurality of intermediate electrodes;
a plurality of first insulating layers between the plurality of gate electrodes; and
a channel layer in contact with the gate insulating layer,
wherein widths of the plurality of intermediate electrodes are greater than widths of the plurality of ferroelectric layers in contact with the plurality of intermediate electrodes, wherein
the plurality of first insulating layers and the plurality of gate electrodes are alternately arranged over the substrate with the plurality of ferroelectric layers separating the plurality of first insulating layers and the plurality of gate electrodes from each other, respectively, and
wherein the plurality of first insulating layers are spaced apart from the gate insulating layer.
2 . The 3D ferroelectric memory device of claim 1 , wherein
the plurality of gate electrodes are stacked in a direction perpendicular to a surface of the substrate, and
each of the plurality of gate electrodes extend in a direction parallel to the surface of the substrate.
3 . The 3D ferroelectric memory device of claim 2 , wherein
the plurality of ferroelectric layers are on upper surfaces of the plurality of gate electrodes and lower surfaces of the plurality of gate electrodes, respectively,
the upper surfaces of the plurality of gate electrodes and the lower surfaces of the plurality of gate electrodes are parallel to the surface of the substrate,
the plurality of gate electrodes include first side surfaces and second side surfaces that are different from each other,
the plurality of ferroelectric layers are on the first side surfaces of the plurality of gate electrodes, and p 1 the first side surfaces are perpendicular to the surface of the substrate.
4 . The 3D ferroelectric memory device of claim 1 , wherein areas of the plurality of ferroelectric layers in contact with the plurality of intermediate electrodes are less than areas of the gate insulating layer in contact with the plurality of intermediate electrodes.
5 . The 3D ferroelectric memory device of claim 1 , wherein the widths of the plurality of intermediate electrodes are about 1.2 times to about 5 times the widths of the plurality of ferroelectric layers in contact with the plurality of intermediate electrodes.
6 . The 3D ferroelectric memory device of claim 5 , wherein the widths of the plurality of intermediate electrodes are about 15 nm to about 100 nm.
7 . The 3D ferroelectric memory device of claim 1 , wherein each of the plurality of gate electrodes and each of the plurality of intermediate electrodes independently include at least one of W, TiN, TaN, WN, NbN, Mo, Ru, Ir, RuO, IrO, and polysilicon.
8 . The 3D ferroelectric memory device of claim 1 , wherein the plurality of first insulating layers comprise at least one of SiO, SiOC, and SiON.
9 . The 3D ferroelectric memory device of claim 1 , wherein the plurality of first insulating layers have thicknesses of about 7 nm to about 100 nm.
10 . The 3D ferroelectric memory device of claim 1 , wherein the plurality of ferroelectric layers comprise a fluorite-based material, a nitride-based material, or perovskite.
11 . The 3D ferroelectric memory device of claim 1 , wherein the plurality of ferroelectric layers have thicknesses of about 3 nm to about 20 nm.
12 . The 3D ferroelectric memory device of claim 1 , further comprising:
a plurality of second insulating layers between the plurality of intermediate electrodes,
wherein insulating materials of the plurality of second insulating layers and the plurality of first insulating layers are different from each other.
13 . The 3D ferroelectric memory device of claim 1 , further comprising:
a plurality of second insulating layers between the plurality of intermediate electrodes, wherein the plurality of second insulating layers comprise SiN.
14 . The 3D ferroelectric memory device of claim 1 , further comprising:
a plurality of second insulating layers between the plurality of intermediate electrodes,
wherein widths of the plurality of second insulating layers are about 5 nm to about 20 nm.
15 . The 3D ferroelectric memory device of claim 1 , wherein the gate insulating layer comprises at least one of SiO, SiN, AIO, HfO, and ZrO.
16 . The 3D ferroelectric memory device of claim 1 , wherein the channel layer commonly corresponds to the plurality of gate electrodes.
17 . The 3D ferroelectric memory device of claim 16 , wherein the channel layer extends in a direction perpendicular to a surface of the substrate.
18 . The 3D ferroelectric memory device of claim 16 , wherein the channel layer comprises a Group IV semiconductor, a Group III-V semiconductor, an oxide semiconductor, a nitride semiconductor, an oxynitride semiconductor, a two-dimensional (2D) semiconductor material, quantum dots, or an organic semiconductor.
19 . A three-dimensional (3D) ferroelectric memory device comprising:
a substrate;
a plurality of gate electrodes stacked on the substrate;
a plurality of ferroelectric layers in contact with the plurality of gate electrodes;
a plurality of intermediate electrodes in contact with the plurality of ferroelectric layers;
a gate insulating layer in contact with the plurality of intermediate electrodes;
a plurality of insulating layers between the plurality of intermediate electrodes such that the plurality of insulating layers and the plurality of intermediate electrodes are alternately arranged in a direction vertical to the substrate; and
a channel layer in contact with the gate insulating layer,
wherein widths of the plurality of intermediate electrodes are greater than widths of the plurality of ferroelectric layers in contact with the plurality of intermediate electrodes.
20 . The 3D ferroelectric memory device of claim 19 ,
wherein areas of the plurality of ferroelectric layers in contact with the plurality of intermediate electrodes are less than areas of the gate insulating layer in contact with the plurality of intermediate electrodes.