Electronic device with galvanic isolation and integration methods

Inventors: Bong Woong Mun (Singapore, SG); Juan Boon Tan (Singapore, SG); Szu Huat Goh (Singapore, SG); Jeoung Mo Koo (Singapore, SG)

Assignee: GlobalFoundries Singapore Pte. Ltd.

H10D1/042 H10D1/716 H10W20/496 H10W44/601 H10W70/05 H10W70/095 H10W70/611 H10W70/65 H10W70/685 H10W72/00 H10W74/016 H10W74/117 H10W90/00 H10W90/701 H10W70/635 H10W90/293

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Quick Facts

Patent No.: US 12677427
App. No.: 17/659,834
Granted: Jul 7, 2026
Kind: B2

External Links

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Abstract

An electronic device is provided, the device comprising an interposer including a dielectric material and an interconnect structure. An integrated circuit chip may be arranged over the interposer. A galvanic capacitor may be spaced from the integrated circuit chip. The galvanic capacitor having a first electrode and a second electrode. The first electrode of the galvanic capacitor may be coupled to the integrated circuit chip. A molding material may be arranged over the integrated circuit chip and the galvanic capacitor, whereby the integrated circuit chip may be spaced from the galvanic capacitor by at least a portion of the molding material.

Claims (31)

1 . An electronic device comprising:

an interposer including a dielectric material and an interconnect structure;

an integrated circuit chip over the interposer;

a galvanic capacitor spaced from the integrated circuit chip, the galvanic capacitor having a first electrode and a second electrode, and the first electrode of the galvanic capacitor is coupled to the integrated circuit chip; and

a molding material over the integrated circuit chip and the galvanic capacitor, wherein the integrated circuit chip is spaced from the galvanic capacitor by at least a portion of the molding material,

wherein the first electrode of the galvanic capacitor is a first conductive plate and the second electrode of the galvanic capacitor is a second conductive plate arranged below the first conductive plate and at least partially underlapping the first conductive plate, the first conductive plate is arranged over and external to the interposer, and the second conductive plate is disposed in the interposer, wherein the first conductive plate is in a second chip laterally adjacent to the integrated circuit chip, and the second conductive plate in the interposer directly contacts the second chip.

2 . The electronic device of claim 1 , further comprising an interconnect pillar connecting the first conductive plate to the interposer, wherein the interconnect pillar extends from a bottom surface of the first conductive plate to a top surface of the interposer.

3 . The electronic device of claim 1 , wherein the second conductive plate is arranged completely in the interposer and is laterally spaced from the integrated circuit chip.

4 . The electronic device of claim 1 , wherein the electronic device is a fan-out package.

5 . The electronic device of claim 4 , wherein the interconnect structure includes an interconnect via, and the interconnect via couples the second electrode of the galvanic capacitor to a package contact.

6 . An electronic device comprising:

an interposer including a dielectric material and an interconnect structure;

an integrated circuit chip over the interposer;

a galvanic capacitor laterally spaced from the integrated circuit chip, the galvanic capacitor having a first electrode and a second electrode, and the first electrode of the galvanic capacitor is electrically coupled to the integrated circuit chip; and

wherein the first electrode of the galvanic capacitor is a first conductive plate and the second electrode of the galvanic capacitor is a second conductive plate arranged below the first conductive plate and at least partially underlapping the first conductive plate, the first conductive plate is arranged over and external to the interposer, and the second conductive plate is disposed in the interposer, wherein the first conductive plate is in a second chip on the interposer and laterally adjacent to the integrated circuit chip, and the second conductive plate in the interposer directly contacts the second chip.

7 . A method of fabricating an electronic device comprising:

forming a molding material over an integrated circuit chip;

forming a galvanic capacitor, the galvanic capacitor having a first electrode and a second electrode, the first electrode of the galvanic capacitor is coupled to the integrated circuit chip, and the galvanic capacitor is spaced from the integrated circuit chip by at least a portion of the molding material; and

forming an interposer including a dielectric material and an interconnect structure, wherein the interposer is below the integrated circuit chip,

wherein the first electrode of the galvanic capacitor is a first conductive plate and the second electrode of the galvanic capacitor is a second conductive plate formed below the first conductive plate and at least partially underlapping the first conductive plate, the first conductive plate is formed over and external to the interposer, and the second conductive plate is formed in the interposer, wherein the first conductive plate is formed in a second chip, the second chip is disposed laterally adjacent to the integrated circuit chip, and the second conductive plate in the interposer directly contacts the second chip.

8 . The electronic device of claim 1 , wherein a surface of the second conductive plate and a top surface of the interposer is substantially coplanar.

9 . The electronic device of claim 2 , wherein the first conductive plate is a single layer and the interconnect pillar extends continuously from the bottom surface of the first conductive plate and through the second chip to a bottom surface of the second chip.

10 . The electronic device of claim 9 , wherein a portion of the dielectric material of the interposer surrounds the second conductive plate and contacts the bottom surface of the second chip.

11 . The electronic device of claim 9 , wherein the second chip is surrounded by the molding material.

12 . The electronic device of claim 2 , wherein the interconnect structure includes an interconnect metal, an interconnect feature, and an interconnect line, wherein the interconnect metal is arranged below the interconnect pillar and the interconnect line is coupled to the interconnect metal by the interconnect feature.

13 . The electronic device of claim 12 , wherein the second conductive plate is laterally spaced from the interconnect metal by a portion of the dielectric material of the interposer.

14 . The electronic device of claim 1 , wherein the interconnect structure includes an interconnect via underlapping the second conductive plate, and the interconnect via couples the second conductive plate to a package contact disposed on a bond pad on the interposer.

15 . The electronic device of claim 14 , wherein the second conductive plate is a single layer and the interconnect via extends continuously from the second conductive plate and through the dielectric material of the interposer to contact the bond pad below the dielectric material of the interposer.

16 . The electronic device of claim 14 , wherein the interconnect structure further includes an interconnect metal and a second interconnect via underlapping the integrated circuit chip, and the second interconnect via couples the integrated circuit chip to another package contact.

17 . The electronic device of claim 16 , wherein the second interconnect via extends from the interconnect metal and through the dielectric material of the interposer to contact another bond pad below the dielectric material of the interposer.