Semiconductor structure and fabrication method thereof
View Patent ↗A semiconductor structure and its fabrication method are provided. The semiconductor structure includes: a substrate, composite layers, a gate structure crossing the composite layers; inner spacers, source/drain layers, and insulating layers. Each composite layer includes channel layers, first openings between the channel layers and the substrate, and second openings between adjacent channel layers. The gate structure is located on sidewalls and top surfaces of the composite layers, and is also located in the second openings and surrounds the channel layers. The inner spacers are located between adjacent channel layers, and between the channel layers and the substrates. The source/drain layers are located in the composite layers on two sides of the gate structure. Sidewalls of the source/drain layers are coplanar with the sidewalls of adjacent inner spacers and end faces of adjacent channel layers. The insulating layers are located in the first openings.
1 . A semiconductor structure, comprising:
a composite layer over a substrate, wherein the composite layer includes a plurality of channel layers stacked along a vertical direction with respect to the substrate;
a gate structure formed over a bottom channel layer of the plurality of channel layers and around each of other channel layers of the plurality of channel layers;
first inner spacers formed on sides of a first portion of the gate structure between adjacent channel layers; and
an isolation structure formed between the bottom channel layer and the substrate, wherein the isolation structure includes an insulating layer sandwiched between second inner spacers formed between the bottom channel layer and the substrate.
2 . The structure according to claim 1 , further comprising:
an interlayer dielectric layer located on the substrate, on a top surface of the composite layer, and on sidewalls of the gate structure.
3 . The structure according to claim 1 , further comprising:
a gate oxide layer and a gate dielectric layer on a surface of the gate oxide layer, wherein the gate structure includes a gate located on a surface of the gate dielectric layer.
4 . The structure according to claim 3 , wherein:
the gate oxide layer and the gate dielectric layer are further located on the insulating layer.
5 . A fabrication method of a semiconductor structure, comprising:
providing a substrate;
forming a composite layer on the substrate, wherein the composite layer includes a plurality of channel layers stacked along a vertical direction with respect to the substrate;
forming a gate structure over a bottom channel layer of the plurality of channel layers and around each of other channel layers of the plurality of channel layers;
forming first inner spacers on sides of a first portion of the gate structure between adjacent channel layers; and
forming an isolation structure between the bottom channel layer and the substrate, wherein the isolation structure includes an insulating layer sandwiched between second inner spacers formed between the bottom channel layer and the substrate.
6 . The structure according to claim 1 , wherein:
in the vertical direction, the insulating layer has a first size, and a portion of the gate structure between adjacent channel layers has a second size, wherein the first size is smaller than the second size.
7 . The structure according to claim 1 , wherein:
the gate structure is located on a portion of surfaces of sidewalls and a top surface of the composite layer, and is also located between adjacent channel layers and surrounds the plurality of channel layers.
8 . The structure according to claim 1 , wherein:
the first inner spacers are located between adjacent channel layers, and the second spacers are located between the bottom channel layer and the substrate.
9 . The structure according to claim 8 , wherein:
the first inner spacers are further located on sidewalls of the gate structure between adjacent channel layers.
10 . The structure according to claim 8 , further comprising a source/drain layer, wherein the source/drain layer is located in the composite layer on two sides of the gate structure.
11 . The structure according to claim 10 , wherein side walls of the source/drain layer are coplanar with sidewalls of adjacent first inner spacers and end faces of adjacent channel layers.
12 . The structure according to claim 1 , wherein the insulating layer is made of silicone oxide.
13 . The structure according to claim 1 , wherein the insulating layer is made of a dielectric material with a relative permittivity higher than 3.9.
14 . The structure according to claim 1 , wherein the insulating layer is made of silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, silicon oxycarbide, or a combination thereof.
15 . The structure according to claim 3 , wherein the insulating layer includes the gate oxide layer and the gate dielectric layer.
16 . The structure according to claim 1 , further comprising an isolation layer formed in the substrate.
17 . The structure according to claim 1 , wherein the first inner spacers and the second inner spacers are aligned with each other along the vertical direction.
18 . The structure according to claim 1 , wherein the first portion of the gate structure between the adjacent channel layers are aligned with the insulating layer between the bottom channel layer and the substrate along the vertical direction.
19 . The structure according to claim 1 , wherein along the vertical direction, a sidewall surface of the first portion of the gate structure between the adjacent channel layers is coplanar with a corresponding sidewall surface of the insulating layer of the isolation structure between the bottom channel layer and the substrate.
20 . The structure according to claim 1 , further comprising a source/drain layer at least located on each side of the isolation structure over the substrate.