Co-integrated resonant tunneling diode and high-electron mobility transistor
One or more devices and/or methods provided herein relate to a method for fabricating a semiconductor device having a co-integrated RTD and HEMT. A semiconductor device can comprise an RTD and an HEMT that are co-integrated along a substrate. A fabrication method can comprise providing a heterostructure comprising a plurality of transistor layers of an HEMT, forming on the vertical stack a template structure comprising an opening, a cavity and a seed structure, the seed structure comprising a seed material and a seed surface, and growing a plurality of diode layers of an RTD within the cavity of the template structure from the seed surface, wherein the RTD and HEMT are co-integrated along a substrate.
1 . A semiconductor device comprising:
a substrate;
a buffer layer on the substrate; and
a resonant tunneling diode (RTD) and a high-electron-mobility transistor (HEMT) that are co-integrated along the substrate,
wherein the RTD is directly adjacent to the HEMT,
wherein the HEMT comprises a first group of layers stacked on the buffer layer,
wherein the first group of layers comprise a channel layer, a barrier layer, a source cap layer and a drain cap layer,
wherein the first group of layers is stacked vertically in a normal direction from a surface of the buffer layer, and
wherein the RTD comprises a second group of layers stacked on a dielectric layer that is parallel to the surface of the buffer layer,
wherein the second group of layers is not in direct contact with the channel layer and the barrier layer,
wherein the second group of layers is stacked horizontally in a parallel direction to the surface of the buffer layer,
wherein a layer at one end of the first group of layers of the HEMT is directly adjacent to a layer at one end of the second group of layers of the RTD, and
wherein the dielectric layer is directly adjacent to the layer at the one end of the first group of layers of the HEMT.
2 . The semiconductor device according to claim 1 , wherein the second group of layers comprise a collector layer, a first quantum well layer, a second quantum well layer and an emitter layer.
3 . The semiconductor device according to claim 2 , wherein the layer at the one end of the second group of layers of the RTD is the emitter layer or the collector layer of the RTD.
4 . The semiconductor device according to claim 2 , wherein the barrier layer is a first barrier layer, and wherein the second group of layers further comprise a second barrier layer between the first quantum well layer and the second quantum well layer.
5 . The semiconductor device according to claim 4 , wherein the second group of layers further comprise a third barrier layer between the first quantum well layer and the emitter layer.
6 . The semiconductor device according to claim 4 , wherein the second group of layers further comprise a third barrier layer between the first quantum well layer and the collector layer.
7 . The semiconductor device according to claim 2 , wherein the barrier layer is a first barrier layer, and wherein the second group of layers further comprise a second barrier layer between the first quantum well layer and the second quantum well layer, a third barrier layer between the first quantum well layer and the collector layer, and fourth barrier layer between the second quantum well layer and the emitter layer.
8 . The semiconductor device according to claim 1 , wherein the layer at the one end of the first group of layers of the HEMT is the drain cap layer or the source cap layer of the HEMT.
9 . The semiconductor device according to claim 1 , wherein the semiconductor device is configured to generate a signal pulse as a qubit control pulse.
10 . The semiconductor device according to claim 1 , wherein the HEMT is a III-V compound transistor comprising a periodic group III-V semiconductor material, and wherein the periodic group III-V semiconductor material comprises a periodic group III element and a periodic group V element.
11 . The semiconductor device according to claim 1 , wherein the RTD is a III-V resonant tunneling diode comprising a periodic group III-V semiconductor material, and wherein the periodic group III-V semiconductor material comprises a periodic group III element and a periodic group V element.
12 . The semiconductor device according to claim 1 , wherein the substrate is a III/V-substrate.
13 . The semiconductor device according to claim 1 , wherein the semiconductor device is arranged inside a cryostat of a quantum computer.
14 . The semiconductor device according to claim 1 , wherein the dielectric layer comprises silicon dioxide.
15 . The semiconductor device according to claim 1 , wherein the buffer layer comprises indium aluminum arsenide.
16 . The semiconductor device according to claim 1 , wherein the channel layer is in direct contact with the buffer layer.
17 . The semiconductor device according to claim 1 , wherein the barrier layer is in direct contact with the channel layer.
18 . The semiconductor device according to claim 1 , wherein the barrier layer is in direct contact with the source cap layer and the drain cap layer.
19 . The semiconductor device according to claim 1 , further comprising a gate structure between the source cap layer and the drain cap layer.
20 . The semiconductor device according to claim 1 , further comprising a first contact layer in direct contact with the RTD, and a second contact layer in direct contact with the HEMT.