Semiconductor devices with selectively doped gate electrode structure
Semiconductor devices including selectively doped gate electrodes are described. The semiconductor device comprises a substrate including a body region and a drift region, a gate dielectric layer on the substrate, the gate dielectric layer extending over the body region and the drift region, and a field relief dielectric layer on the drift region, the field relief dielectric layer laterally abutting the gate dielectric layer at a location over the drift region. The semiconductor device also includes a gate electrode having an n-doped first portion, a p-doped second portion, and an n-doped third portion. The selectively doped second portion of the gate electrode is located over an intersection between the gate dielectric layer and the field relief dielectric layer.
1 . A semiconductor device, comprising:
a substrate including a body region having a first conductivity type and a drift region having a second conductivity type opposite the first conductivity type;
a gate dielectric layer on the substrate, the gate dielectric layer extending over the body region and the drift region;
a field relief dielectric layer on the drift region, the field relief dielectric layer laterally abutting the gate dielectric layer at a location over the drift region;
a gate electrode on the gate dielectric layer and the field relief dielectric layer, the gate electrode including;
a first portion with the second conductivity type, and extending over the body region and a first part of the drift region;
a second portion with the first conductivity type, abutting the first portion, and extending over a second part of the drift region and a first part of the field relief dielectric layer, the second portion having a center midline approximately corresponding to an intersection point between the gate dielectric layer and the field relief dielectric layer at the location over the drift region; and
a third portion with the second conductivity type, abutting the second portion, and extending over a second part of the field relief dielectric layer;
a source region disposed in the body region, the source region having the second conductivity type; and
a drain region disposed in the drift region, the drain region having the second conductivity type.
2 . The semiconductor device of claim 1 , wherein a width of the second portion of the gate electrode is at least twice a thickness of the gate electrode, the width corresponding to a distance between the first portion and the third portion of the gate electrode.
3 . The semiconductor device of claim 1 , wherein a width of the second portion of the gate electrode is greater than 300 nanometers, the width corresponding to a distance between the first portion and the third portion of the gate electrode.
4 . The semiconductor device of claim 1 , wherein the second portion of the gate electrode is degenerately doped or has an active average dopant density greater than 1×10 19 /cm 3 .
5 . The semiconductor device of claim 1 , wherein the field relief dielectric layer includes silicon dioxide of a local oxidation of silicon (LOCOS) layer.
6 . The semiconductor device of claim 1 , wherein the first conductivity type is p-type and the second conductivity type is n-type.
7 . The semiconductor device of claim 1 , wherein the gate electrode has a racetrack layout.
8 . The semiconductor device of claim 1 , wherein:
the gate dielectric layer has a first thickness; and
the field relief dielectric layer has a second thickness greater than the first thickness.
9 . The semiconductor device of claim 1 , wherein:
the source region has a first average dopant density greater than a second average dopant density of the body region; and
the drain region has the first average dopant density greater than a fourth average dopant density of the drift region.
10 . The semiconductor device of claim 1 , further comprising:
a back-gate region disposed in the body region, the back-gate region having the first conductivity type, wherein the back-gate region is electrically isolated and separated from the source region.
11 . The semiconductor device of claim 1 , wherein the field relief dielectric layer is a shallow trench isolation structure at least partially disposed within the substrate.
12 . The semiconductor device of claim 1 , further comprising a sidewall spacer disposed along a sidewall of the gate electrode; and
wherein the first portion of the gate electrode extends laterally from the sidewall spacer to over the body region and the first part of the drift region such that the first portion of the gate electrode extends laterally over more of the first part of the drift region than the body region.
13 . A method, comprising:
forming a field relief dielectric layer on a substrate;
forming a body region and a drift region in the substrate, the body region having a first conductivity type and the drift region having a second conductivity type opposite the first conductivity type;
forming a gate dielectric layer on the substrate, the gate dielectric layer extending over the body region and the drift region, the gate dielectric layer laterally abutting the field relief dielectric layer at a location over the drift region;
forming a gate electrode on the gate dielectric layer and the field relief dielectric layer, the gate electrode including;
a first portion with the second conductivity type, and extending over the body region and a first part of the drift region;
a second portion with the first conductivity type, abutting the first portion, and extending over a second part of the drift region and a first part of the field relief dielectric layer, the second portion having a center midline approximately corresponding to an intersection point between the gate dielectric layer and the field relief dielectric layer at the location over the drift region; and
a third portion with the second conductivity type, abutting the second portion, and extending over a second part of the field relief dielectric layer;
forming a source region in the body region, the source region having the second conductivity type; and
forming a drain region in the drift region, the drain region having the second conductivity type.
14 . The method of claim 13 , wherein a width of the second portion of the gate electrode is at least twice a thickness of the gate electrode, the width corresponding to a distance between the first portion and the third portion of the gate electrode.
15 . The method of claim 13 , wherein the second portion of the gate electrode is degenerately doped or has an active average dopant density greater than 1×10 19 /cm 3 .
16 . The method of claim 13 , further comprising:
forming a back-gate region in the body region, the back-gate region having the first conductivity type, wherein the back-gate region is electrically isolated and separated from the source region.
17 . The method of claim 16 , wherein forming the back-gate region includes forming the second portion of the gate electrode.
18 . A semiconductor device, comprising:
a substrate including a p-type body region and an n-type drift region;
a first dielectric layer on the substrate, the first dielectric layer extending over the p-type body region and the n-type drift region;
a second dielectric layer on the n-type drift region, the second dielectric layer having a thickness greater than the first dielectric layer, and laterally abutting the first dielectric layer at a location over the n-type drift region;
a gate electrode on the first dielectric layer and the second dielectric layer, the gate electrode including;
an n-type first portion extending over the p-type body region and a first part of the n-type drift region;
a p-type second portion abutting the n-type first portion, and extending over a second part of the n-type drift region and a first part of the second dielectric layer, the p-type second portion having a center midline approximately corresponding to an intersection point between the first dielectric layer and the second dielectric layer at the location over the n-type drift region; and
an n-type third portion, abutting the p-type second portion, and extending over a second part of the second dielectric layer;
an n-type source region disposed in the p-type body region; and
an n-type drain region disposed in the n-type drift region.
19 . The semiconductor device of claim 18 , wherein the p-type second portion of the gate electrode has an active average dopant density greater than 1×10 19 /cm 3 .
20 . The semiconductor device of claim 18 , wherein:
the second dielectric layer is a local oxidation of silicon (LOCOS) layer including a bird's beak; and
the bird's beak terminating at the intersection point between the first dielectric layer and the second dielectric layer.