IP Library Granted Patent US 12677442
Granted Patent B2
US 12677442 · App. 18/243,818 · Granted Jul 7, 2026

Semiconductor device

Inventors: Wandon Kim (Suwon-si, KR); Jaeseoung Park (Suwon-si, KR); Hyunwoo Kim (Suwon-si, KR); Hyunbae Lee (Suwon-si, KR); Jeonghyuk Yim (Suwon-si, KR); Hyoseok Choi (Suwon-si, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
H10D30/6729H10D30/43H10D30/6735H10D30/6757H10D62/121H10D64/258
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Quick Facts
Patent No.
US 12677442
App. No.
18/243,818
Granted
Jul 7, 2026
Kind
B2
Abstract

A semiconductor device includes an active region extending in a first direction, a gate structure extending in a second direction, a source/drain region on the active region, a first contact structure connected to the source/drain region, and a second contact structure connected to the first contact structure. The second contact structure includes a first layer including a first grain and a second layer including second grains on the first layer. Within the first layer, a maximum vertical distance between a lowermost end of the first grain and an uppermost end of the first grain is equal to a vertical distance between a lowermost end of the first layer and an uppermost end of the first layer. A size of the first grain is greater than a size of each of the second grains. A width of the first layer is greater than a width of the first contact structure.

Claims (51)

1 . A semiconductor device comprising:

an active region extending in a first direction on a substrate;

a gate structure extending in a second direction on the substrate, crossing the active region, and including a gate electrode;

a source/drain region on the active region on at least one side of the gate structure; a first contact structure connected to the source/drain region on the at least one side of the gate structure; and

a second contact structure connected to the first contact structure and disposed on the first contact structure,

wherein the second contact structure includes a first layer including a first grain and a second layer including second grains on the first layer,

wherein the first layer is disposed between the second layer and the first contact structure,

wherein within the first layer, a maximum vertical distance between a lowermost end of the first grain and an uppermost end of the first grain is equal to a vertical distance between a lowermost end of the first layer and an uppermost end of the first layer, wherein a size of the first grain is greater than a size of each of the second grains, and

wherein a width of the first layer is greater than a width of the first contact structure.

2 . The semiconductor device of claim 1 , wherein the first layer includes a monocrystalline molybdenum layer, and the second layer includes a polycrystalline molybdenum layer.

3 . The semiconductor device of claim 1 , wherein the first layer has a convex surface in contact with the second layer.

4 . The semiconductor device of claim 1 , wherein the size of each of the at least one first grain is about 5 nm or more.

5 . The semiconductor device of claim 1 , wherein: the first layer includes two or less of the first grain, and the number of the second grains is three or more.

6 . The semiconductor device of claim 1 , further comprising: a void between at least two of the second grains.

7 . The semiconductor device of claim 1 , wherein a first length between an upper end of the first layer and a lower end of the first layer is greater than a second length between an upper end of the second layer and a lower end of the second layer.

8 . The semiconductor device of claim 1 , wherein a width of the first layer is within a range of about 5 nm to about 20 nm.

9 . The semiconductor device of claim 1 , wherein the first contact structure includes a metal-semiconductor compound layer in a recess region of the source/drain region, a plug conductive layer on the metal-semiconductor compound layer, and a barrier layer covering a lower surface and side surfaces of the plug conductive layer.

10 . The semiconductor device of claim 9 , wherein the first layer is in contact with an upper surface of the plug conductive layer and the barrier layer.

11 . The semiconductor device of claim 1 , further comprising:

a plurality of channel layers on the active region spaced apart from each other in a vertical direction, perpendicular to an upper surface of the substrate,

wherein the gate crosses the plurality of channel layers on the substrate, surrounds a portion of each of the plurality of channel layers, and extends in the second direction.

12 . A semiconductor device comprising:

an active region extending in a first direction on a substrate;

a gate structure extending in a second direction on the substrate, crossing the active region, and including a gate electrode;

a source/drain region disposed on the active region on at least one side of the gate structure;

a first contact structure connected to the source/drain region on the at least one side of the gate structure; and

a second contact structure connected to the first contact structure and disposed on the first contact structure,

wherein the second contact structure includes a first layer including a first grain and a second layer including second grains and disposed on the first layer,

wherein the first layer is disposed between the second layer and the first contact structure,

wherein the first layer includes a monocrystalline conductive material, wherein the second layer includes a polycrystalline conductive material, and

wherein a size of the first grain is greater than a size of each of the second grains.

13 . The semiconductor device of claim 12 , wherein an extension line of a side surface of the first layer and an extension line of a side surface of the second layer meet each other.

14 . The semiconductor device of claim 12 , wherein:

the second layer includes a seam between at least two of the second grains, and the seam is positioned on a level higher than that of a boundary between the first layer and the second layer.

15 . The semiconductor device of claim 12 , wherein a first width of a lower portion of the first layer is greater than a second width of an upper portion of the first contact structure.

16 . The semiconductor device of claim 12 , wherein an uppermost end of the first layer is positioned on a level higher than that of a lowermost end of the second layer.

17 . The semiconductor device of claim 12 , wherein:

each of the first layer and the second layer has an inclined side surface having a lower width becoming narrower than an upper width, and a width of the second layer is greater than a width of the first layer.

18 . The semiconductor device of claim 12 , wherein:

a first length between an upper portion of the first layer and a lower portion of the first layer is within a range of about 3 nm to about 20 nm, and a second length between an upper portion of the second layer and a lower portion of the second layer is within a range of about 3 nm to about 10 nm.

19 . A semiconductor device comprising:

first and second interlayer insulating layers on a substrate;

a first contact structure passing through the first interlayer insulating layer that is on the substrate;

a second contact structure passing through the second interlayer insulating layer, the second contact structure in contact with an upper surface of the first contact structure; and

a metal interconnection in contact with an upper surface of the second contact structure, the metal interconnection extending in a first direction,

wherein the second contact structure includes a first layer including a first grain and a second layer including second grains on the first layer,

wherein the first layer is disposed between the second layer and the first contact structure,

wherein the first layer includes a monocrystalline conductive material,

wherein the second layer includes a polycrystalline conductive material, wherein a size of the first grain is greater than a size of each of the second grains, and

wherein a width of the first layer is greater than a width of the first contact structure.

20 . The semiconductor device of claim 19 , wherein a first length between an upper end of the first layer and a lower end of the first layer is greater than a second length between an upper end of the second layer and a lower end of the second layer.