Self-aligned substrate isolation (SASI) of gate-all-around nanosheet field effect transistors

1 . A semiconductor structure comprising:

a substrate;

a gate-all-around field effect transistor disposed over the substrate, the gate-all-around field effect transistor including:

a first source-drain region;

a second source-drain region;

at least one channel region interconnecting the first and second source-drain regions;

a gate structure surrounding the at least one channel region;

a punch-through stopper implant layer in the substrate below the first and second source-drain regions and the gate structure;

a self-aligned substrate isolation (SASI) layer located between the punch-through stopper implant layer and the gate structure and extending over a width of the gate structure; and

a first doped region adjacent the first source-drain region and a second doped region adjacent the second source-drain region, wherein the first and second doped regions are:

located within the punch-through stopper implant layer;

more highly doped than the punch-through stopper implant layer; and

not extending across the width of the gate structure.

2 . The semiconductor structure of claim 1 , wherein:

the self-aligned substrate isolation (SASI) layer is in contact with the punch-through stopper implant layer.

3 . The semiconductor structure of claim 2 , wherein the gate structure includes:

a metal gate in a gate region;

conformal gate spacers on each side of the metal gate, in an extension region; and

inner spacers on each side of the metal gate, in the extension region.

4 . The semiconductor structure of claim 3 , wherein the self-aligned substrate isolation (SASI) layer and the conformal gate spacers are different materials.

5 . The semiconductor structure of claim 2 , wherein:

the at least one channel region comprises a plurality of channel regions interconnecting the first and second source-drain regions;

the gate structure surrounds the plurality of channel regions; and

the gate structure includes:

a metal gate in a gate region;

conformal gate spacers on each side of the metal gate, in an extension region; and

inner spacers on each side of the metal gate, in the extension region.

6 . The semiconductor structure of claim 5 , wherein an outer surface of the substrate is flat, continuous, and does not exhibit substantial topography changes between a portion of the outer surface adjacent the first and second source-drain regions and a portion of the outer surface adjacent the gate structure.

7 . The semiconductor structure of claim 5 , wherein an outer surface of the substrate is flat, continuous, and does not have a recess.

8 . The semiconductor structure of claim 5 , wherein the first and second source-drain regions directly contact an outer surface of the first and second doped regions, respectfully, and do not extend more than 5 nm below a lower surface of the self-aligned substrate isolation (SASI) layer.

9 . The semiconductor structure of claim 5 , wherein the first and second source-drain regions directly contact an outer surface of the first and second doped regions, respectfully, and do not extend more than 10 nm below a lower surface of the self-aligned substrate isolation (SASI) layer.

10 . The semiconductor structure of claim 5 , wherein the first and second source-drain regions directly contact an outer surface of the first and second doped regions, respectfully, and do not extend below a lower surface of the self-aligned substrate isolation (SASI) layer.

11 . The semiconductor structure of claim 2 , wherein the first and second doped regions are of a same doping polarity as the punch-through stopper implant layer.

12 . A semiconductor array structure comprising:

a substrate;

a plurality of P-type gate-all-around field effect transistors disposed over the substrate, each P-type gate-all-around field effect transistor including:

a first P-type source-drain region;

a second P-type source-drain region;

at least one PFET channel region interconnecting the first and second P-type source-drain regions; and

a PFET gate structure surrounding the at least one PFET channel region;

a plurality of N-type gate-all-around field effect transistors disposed over the substrate, each N-type gate-all-around field effect transistor including:

a first N-type source-drain region;

a second N-type source-drain region;

at least one NFET channel region interconnecting the first and second N-type source-drain regions; and

an NFET gate structure surrounding the at least one NFET channel region;

a plurality of N-type punch-through stopper implant layers in the substrate below the P-type source-drain regions and the PFET gate structures;

a plurality of P-type punch-through stopper implant layers in the substrate below the N-type source-drain regions and the NFET gate structures;

a plurality of carbon-bearing leakage control layers in the substrate below the P-type source-drain regions and the PFET gate structures and below the N-type source-drain regions and the NFET gate structures;

a first plurality of self-aligned substrate isolation (SASI) layers located between the carbon-bearing leakage control layers in the substrate and the NFET gate structures and extending over a width of the NFET gate structures; and

a second plurality of self-aligned substrate isolation (SASI) layers located between the carbon-bearing leakage control layers in the substrate and the PFET gate structures and extending over a width of the PFET gate structures.

13 . The semiconductor structure of claim 12 , wherein the first and second N-type and P-type source-drain regions extend past a lower surface of the first plurality and second plurality of self-aligned substrate isolation (SASI) layers, respectively, into the plurality of carbon-bearing leakage control layers.

14 . A hardware description language (HDL) design structure encoded on a machine-readable data storage medium, said HDL design structure comprising elements that when processed in a computer-aided design system generate a machine-executable representation of a semiconductor array structure, wherein said HDL design structure comprises:

a substrate;

a plurality of P-type gate-all-around field effect transistors disposed over the substrate, each P-type gate-all-around field effect transistor including:

a first P-type source-drain region;

a second P-type source-drain region;

at least one PFET channel region interconnecting the first and second P-type source-drain regions; and

a PFET gate structure surrounding the at least one PFET channel region;

a plurality of N-type gate-all-around field effect transistors disposed over the substrate, each N-type gate-all-around field effect transistor including:

a first N-type source-drain region;

a second N-type source-drain region;

at least one NFET channel region interconnecting the first and second N-type source-drain regions; and

an NFET gate structure surrounding the at least one NFET channel region;

a first plurality of super-steep retrograde well (SSRW) layers in the substrate below the N-type source-drain regions and the NFET gate structures;

a second plurality of super-steep retrograde well (SSRW) layers in the substrate below the P-type source-drain regions and the PFET gate structures;

a plurality of P-type punch-through stopper implant layers in the substrate below the first plurality of super-steep retrograde well (SSRW) layers;

a plurality of N-type punch-through stopper implant layers in the substrate below the second plurality of super-steep retrograde well (SSRW) layers;

a first plurality of self-aligned substrate isolation (SASI) layers located between the first plurality of super-steep retrograde well (SSRW) layers in the substrate and the NFET gate structures and extending over a width of the NFET gate structures; and

a second plurality of self-aligned substrate isolation (SASI) layers located between the second plurality of super-steep retrograde well (SSRW) layers in the substrate and the PFET gate structures and extending over a width of the PFET gate structures.

15 . The semiconductor structure of claim 14 , wherein the first and second N-type and P-type source-drain regions, respectively, extend past an inner surface of the first plurality and second plurality of self-aligned substrate isolation (SASI) layers into the first plurality and second plurality of super-steep retrograde well (SSRW) layers.

16 . The hardware description language (HDL) design structure of claim 14 , wherein:

the plurality of P-type punch-through stopper implant layers and the N-type source-drain regions are in contact with the first plurality of super-steep retrograde well (SSRW) layers; and

the plurality of N-type punch-through stopper implant layers and the P-type source-drain regions are in contact with the second plurality of super-steep retrograde well (SSRW) layers.

17 . A semiconductor array structure comprising:

a substrate;

a plurality of P-type gate-all-around field effect transistors disposed over the substrate, each P-type gate-all-around field effect transistor including:

a first P-type source-drain region;

a second P-type source-drain region;

at least one PFET channel region interconnecting the first and second P-type source-drain regions; and

a PFET gate structure surrounding the at least one PFET channel region;

a plurality of N-type gate-all-around field effect transistors disposed over the substrate, each N-type gate-all-around field effect transistor including:

a first N-type source-drain region;

a second N-type source-drain region;

at least one NFET channel region interconnecting the first and second N-type source-drain regions; and

an NFET gate structure surrounding the at least one NFET channel region;

a plurality of N-type punch-through stopper implant layers in the substrate adjacent an upper surface of the substrate, facing towards the P-type gate-all-around field effect transistors, below the P-type source-drain regions and the PFET gate structures;

a plurality of P-type punch-through stopper implant layers in the substrate adjacent the upper surface of the substrate, facing towards the N-type gate-all-around field effect transistors, below the N-type source-drain regions and the NFET gate structures;

a first plurality of self-aligned substrate isolation (SASI) layers located between the plurality of P-type punch-through stopper implant layers and the NFET gate structures and extending over a width of the NFET gate structures;

a second plurality of self-aligned substrate isolation (SASI) layers located between the plurality of N-type punch-through stopper implant layers and the PFET gate structures and extending over a width of the PFET gate structures;

a plurality of first doped regions in the plurality of P-type punch-through stopper implant layers adjacent the first and second N-type source-drain regions; and

a plurality of second doped regions in the plurality of N-type punch-through stopper implant layers adjacent the first and second P-type source-drain regions,

wherein the plurality of first and second doped regions, respectively, are more highly doped than the P-type and N-type punch-through stopper implant layers and do not extend across the width of the NFET and PFET gate structures.

18 . The semiconductor structure of claim 17 , wherein the PFET and NFET gate structures include:

a metal gate in a gate region;

conformal gate spacers on each side of the metal gate, in an extension region; and

inner spacers on each side of the metal gate, in the extension region.

19 . The semiconductor structure of claim 18 , wherein the first and second plurality of self-aligned substrate isolation (SASI) layers and the conformal gate spacers are different materials.

20 . A hardware description language (HDL) design structure encoded on a machine-readable data storage medium, said HDL design structure comprising elements that when processed in a computer-aided design system generate a machine-executable representation of a semiconductor array structure, wherein said HDL design structure comprises:

a substrate;

a plurality of P-type gate-all-around field effect transistors disposed over the substrate, each P-type gate-all-around field effect transistor including:

a first P-type source-drain region;

a second P-type source-drain region;

at least one PFET channel region interconnecting the first and second P-type source-drain regions; and

a PFET gate structure surrounding the at least one PFET channel region;

a plurality of N-type gate-all-around field effect transistors disposed over the substrate, each N-type gate-all-around field effect transistor including:

a first N-type source-drain region;

a second N-type source-drain region;

at least one NFET channel region interconnecting the first and second N-type source-drain regions; and

an NFET gate structure surrounding the at least one NFET channel region;

a plurality of N-type punch-through stopper implant layers in the substrate adjacent an upper surface of the substrate, facing towards the P-type gate-all-around field effect transistors, below the P-type source-drain regions and the PFET gate structures;

a plurality of P-type punch-through stopper implant layers in the substrate adjacent the upper surface of the substrate, facing towards the N-type gate-all-around field effect transistors, below the N-type source-drain regions and the NFET gate structures;

a first plurality of self-aligned substrate isolation (SASI) layers located between the plurality of P-type punch-through stopper implant layers and the NFET gate structures and extending over a width of the NFET gate structures;

a second plurality of self-aligned substrate isolation (SASI) layers located between the plurality of N-type punch-through stopper implant layers and the PFET gate structures and extending over a width of the PFET gate structures;

a plurality of first doped regions in the plurality of P-type punch-through stopper implant layers adjacent the first and second N-type source-drain regions; and

a plurality of second doped regions in the plurality of N-type punch-through stopper implant layers adjacent the first and second P-type source-drain regions,

wherein the plurality of first and second doped regions, respectively, are more highly doped than the plurality of P-type and N-type punch-through stopper implant layers and do not extend across the width of the NFET and PFET gate structures.

21 . The semiconductor structure of claim 20 , wherein the PFET and NFET gate structures include:

a metal gate in a gate region;

conformal gate spacers on each side of the metal gate, in an extension region; and

inner spacers on each side of the metal gate, in the extension region.

22 . The semiconductor structure of claim 21 , wherein the first and second plurality of self-aligned substrate isolation (SASI) layers and the conformal gate spacers are different materials.