IP Library › Granted Patent US 12677446
Granted Patent B2
US 12677446 · App. 18/675,249 · Granted Jul 7, 2026

Semiconductor device and manufacturing method of the same

Inventors: Satoshi Toriumi (Ebina, JP); Takashi Hamada (Atsugi, JP); Tetsunori Maruyama (Atsugi, JP); Yuki Imoto (Sagamihara, JP); Yuji Asano (Atsugi, JP); Ryunosuke Honda (Atsugi, JP); Shunpei Yamazaki (Tokyo, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H10D30/6755H10B41/70H10D30/6729H10D30/673H10D30/6734H10D30/6739H10D30/6757H10D62/80H10D64/691H10D84/038H10D86/423H10D86/60H10D87/00H10D88/00H10D88/01H10F39/182H10F39/184
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Quick Facts
Patent No.
US 12677446
App. No.
18/675,249
Granted
Jul 7, 2026
Kind
B2
Abstract

A minute transistor is provided that includes a first insulator, a second insulator, a first, conductor, a second conductor, and third conductor, in which an angle is formed between a side surface of the first insulator and a top surface of the first conductor, and a length between the first conductor and a surface of the second conductor closest to the first conductor is at least greater than a length between the first conductor and the third conductor.

Claims (81)

1 . A semiconductor device comprising:

a first transistor;

a second transistor; and

a capacitor,

wherein a first insulator is provided over a substrate,

wherein a first channel formation region of the first transistor is provided over the first insulator,

wherein the first channel formation region comprises silicon,

wherein a second insulator is provided over the first channel formation region,

wherein a first conductor is provided over the second insulator,

wherein the first conductor comprises a region configured to function as a first gate electrode of the first transistor,

wherein a third insulator is provided over the first conductor,

wherein a second conductor is provided over the third insulator,

wherein the second conductor comprises a region configured to function as a second gate electrode of the second transistor,

wherein a fourth insulator is provided over the second conductor,

wherein a layer comprising a second channel formation region of the second transistor is provided over the fourth insulator,

wherein the second channel formation region comprises an oxide semiconductor,

wherein a fifth insulator is provided over the layer comprising the second channel formation region of the second transistor,

wherein a third conductor is provided over the fifth insulator,

wherein the third conductor comprises a region configured to function as a third gate electrode of the second transistor,

wherein a fourth conductor and a fifth conductor are provided over the third conductor,

wherein a sixth insulator is provided over the fourth conductor and the fifth conductor,

wherein a sixth conductor is provided over the sixth insulator,

wherein the fourth conductor comprises a region configured to function as a first electrode of the capacitor,

wherein the sixth conductor comprises a region configured to function as a second electrode of the capacitor, and

wherein the fifth conductor is electrically connected to the layer comprising the second channel formation region of the second transistor.

2 . The semiconductor device according to claim 1 , wherein the fourth conductor is electrically connected to the layer comprising the second channel formation region of the second transistor and the first gate electrode of the first transistor.

3 . A semiconductor device comprising:

a first transistor;

a second transistor; and

a capacitor,

wherein a first insulator is provided over a substrate,

wherein a first channel formation region of the first transistor is provided over the first insulator,

wherein the first channel formation region comprises silicon,

wherein a second insulator is provided over the first channel formation region,

wherein a first conductor is provided over the second insulator,

wherein the first conductor comprises a region configured to function as a first gate electrode of the first transistor,

wherein a third insulator is provided over the first conductor,

wherein a second conductor is provided over the third insulator,

wherein the second conductor comprises a region configured to function as a second gate electrode of the second transistor,

wherein a fourth insulator is provided over the second conductor,

wherein a layer comprising a second channel formation region of the second transistor is provided over the fourth insulator,

wherein the second channel formation region comprises an oxide semiconductor,

wherein a fifth insulator is provided over the layer comprising the second channel formation region of the second transistor,

wherein a third conductor is provided over the fifth insulator,

wherein the third conductor comprises a region configured to function as a third gate electrode of the second transistor,

wherein a fourth conductor and a fifth conductor are provided over the third conductor,

wherein a sixth insulator is provided over the fourth conductor and the fifth conductor,

wherein a sixth conductor is provided over the sixth insulator,

wherein the fourth conductor comprises a region configured to function as a first electrode of the capacitor,

wherein the sixth conductor comprises a region configured to function as a second electrode of the capacitor,

wherein the fourth conductor is electrically connected to one of a source and a drain of the second transistor and the first gate electrode of the first transistor,

wherein the fifth conductor is electrically connected to the other of the source and the drain of the second transistor and one of a source and a drain of the first transistor, and

wherein the fourth conductor and the fifth conductor are formed from a same layer.

4 . A semiconductor device comprising:

a first transistor;

a second transistor; and

a capacitor,

wherein a first insulator is provided over a substrate,

wherein a first channel formation region of the first transistor is provided over the first insulator,

wherein the first channel formation region comprises silicon,

wherein a second insulator is provided over the first channel formation region,

wherein a first conductor is provided over the second insulator,

wherein the first conductor comprises a region configured to function as a first gate electrode of the first transistor,

wherein a third insulator is provided over the first conductor,

wherein a second conductor is provided over the third insulator,

wherein the second conductor comprises a region configured to function as a second gate electrode of the second transistor,

wherein a fourth insulator is provided over the second conductor,

wherein a layer comprising a second channel formation region of the second transistor is provided over the fourth insulator,

wherein the second channel formation region comprises an oxide semiconductor,

wherein a fifth insulator is provided over the layer comprising the second channel formation region of the second transistor,

wherein a third conductor is provided over the fifth insulator,

wherein the third conductor comprises a region configured to function as a third gate electrode of the second transistor,

wherein a fourth conductor, a fifth conductor, and a sixth conductor are provided over the third conductor,

wherein a sixth insulator is provided over the fourth conductor, the fifth conductor, and the sixth conductor,

wherein a seventh conductor is provided over the sixth insulator,

wherein the fourth conductor comprises a region configured to function as a first electrode of the capacitor,

wherein the seventh conductor comprises a region configured to function as a second electrode of the capacitor,

wherein the fourth conductor is electrically connected to the layer comprising the second channel formation region of the second transistor and the first gate electrode of the first transistor,

wherein the fifth conductor is electrically connected to the layer comprising the second channel formation region of the second transistor,

wherein the fourth conductor, the fifth conductor, and the sixth conductor are formed from a same layer, and

wherein the sixth conductor overlaps with the second conductor and the third conductor.