Semiconductor device and manufacturing method thereof

1 . A manufacturing method of a semiconductor device, comprising steps of:

depositing an N-drift layer on a termination area of a substrate;

conducting an ion implant process on the N-drift layer to form a plurality of P-type pillars;

depositing a N-type epitaxial layer on the P-type pillars;

conducting an ion implant process on the N-type epitaxial layer to form a first P-type epitaxial layer and at least one localized P region at a front side of the termination area;

conducting a field oxidation to the first P-type epitaxial layer to form a second P-type epitaxial layer, the field oxidation spreads from the first P-type epitaxial layer to the end of the P-type pillars to form the second P-type epitaxial layer; and

forming a field oxide layer on the first P-type epitaxial layer, the localized P region and the N-type epitaxial layer; wherein the localized P region passes though the N-type epitaxial layer to the field oxide layer, the field oxide layer electrically connects to the second P-type epitaxial layer by the localized P region;

conducting a polysilicon deposition on the first P-type epitaxial layer to form a polysilicon layer at the front side of the termination area, wherein the polysilicon layer abuts against the field oxide;

disposing a source electrode on a side of the polysilicon layer and the first P-type epitaxial layer, wherein the first P-type epitaxial layer extends from the source electrode;

disposing a gate electrode disposed on another side of the polysilicon layer.

2 . The manufacturing method of claim 1 , wherein the step of conducting the ion implant process on the N-drift layer to form the plurality of P-type pillars comprises a step of: conducting the ion implant process on the N-drift layer to form a plurality of P-type regions.

3 . The manufacturing method of claim 2 , wherein the step of conducting the ion implant process on the N-drift layer to form the plurality of P-type pillars further comprises steps of:

(a) depositing a N-type layer on the P-type regions;

(b) conducting the ion implant process on the N-type layer to form the P-type regions;

(c) repeating steps (a)-(b) for at least one time;

(d) conducting a field oxidation to the P-type regions to form the P-type pillars.

4 . The manufacturing method of claim 1 , wherein the localized P region is formed on the second P-type epitaxial layer along a longitudinal direction of one of the P-type pillars.

5 . The manufacturing method of claim 1 , wherein each of the localized P region is spaced apart from each other.

6 . The manufacturing method of claim 1 , wherein a ratio of the localized P region to the P-type pillars is 1:3-100.

7 . The manufacturing method of claim 1 , further comprising a step of electrically conducting the semiconductor device, wherein a peak of a surface electric field of the semiconductor device is approximately equal to or less than 2.1×10 5 V/cm.

8 . The manufacturing method of claim 1 , further comprising a step of electrically conducting the semiconductor device, wherein a breakdown voltage of the semiconductor device is approximately equal to or greater than 1.05 times to device sustained breakdown voltage rating.

9 . The manufacturing method of claim 1 , further comprising steps of:

disposing an equipotential ring electrode on the field oxide.