Bottom dielectric isolation for vertically stacked devices
A first and a second nanosheet stack, a shallow trench isolation region vertically aligned between them, a continuous dielectric layer below the first and second nanosheet stack and above the shallow trench isolation region. The shallow trench isolation region is vertically aligned with a source drain between the first and the second nanosheet stack. A method including forming a first and a second nanosheet stack on a first substrate, the first and the second nanosheet stack each including a lower nanosheet stack vertically aligned above an upper nanosheet stack, the upper nanosheet stack and the lower nanosheet stack each including alternating layers of a sacrificial material and a semiconductor channel material vertically aligned and stacked one on top of another, flipping the first substrate over, bonding an upper surface of the first substrate to an upper surface of a second substrate which includes a shallow trench isolation region.
1 . A semiconductor device comprising:
a first nanosheet stack and a second nanosheet stack on a substrate, wherein the first nanosheet stack and the second nanosheet stack each comprise:
a lower nanosheet stack comprising alternating layers of a first work function metal and a semiconductor channel material vertically aligned and stacked one on top of another; and
an upper nanosheet stack comprising alternating layers of a second work function metal and the semiconductor channel material vertically aligned and stacked one on top of another, the upper nanosheet stack vertically aligned and stacked on top of the lower nanosheet stack;
a shallow trench isolation region in the substrate, the shallow trench isolation region vertically aligned between the first nanosheet stack and the second nanosheet stack, the shallow trench isolation region having a liner on side and bottom surfaces;
a continuous dielectric layer below the first nanosheet stack, below the second nanosheet stack, and above and in direct contact with the shallow trench isolation region; and
a non-continuous dielectric layer below the continuous dielectric layer in direct contact with a side of the liner.
2 . The semiconductor device according to claim 1 , wherein the shallow trench isolation region is below a source drain between the first nanosheet stack and the second nanosheet stack.
3 . The semiconductor device according to claim 1 , further comprising:
a second continuous dielectric layer below the first nanosheet stack, below the second nanosheet stack and above the shallow trench isolation region.
4 . The semiconductor device according to claim 1 , further comprising:
a silicon dioxide (SiO 2 ) layer below the first nanosheet stack bonded to a second silicon dioxide (SiO 2 ) layer above the substrate.
5 . The semiconductor device according to claim 1 , further comprising:
an upper source drain region between the upper nanosheet stack of the first nanosheet stack and the upper nanosheet stack of the second nanosheet stack; and
a lower source drain region between the lower nanosheet stack of the first nanosheet stack and the lower nanosheet stack of the second nanosheet stack.
6 . The semiconductor device according to claim 5 , further comprising:
an interlayer dielectric physically separating the upper source drain region and the lower source drain region.
7 . A semiconductor device comprising:
a first nanosheet stack and a second nanosheet stack on a substrate, wherein the first nanosheet stack and the second nanosheet stack each comprise:
a lower nanosheet stack comprising alternating layers of a first work function metal and a semiconductor channel material vertically aligned and stacked one on top of another; and
an upper nanosheet stack comprising alternating layers of a second work function metal and the semiconductor channel material vertically aligned and stacked one on top of another, the upper nanosheet stack vertically aligned and stacked on top of the lower nanosheet stack;
a shallow trench isolation region in the substrate, the shallow trench isolation region vertically aligned between the first nanosheet stack and the second nanosheet stack, the shallow trench isolation region having a liner on side and bottom surfaces;
a continuous dielectric layer below the first nanosheet stack, below the second nanosheet stack, and above and in direct contact with the shallow trench isolation region; and
a non-continuous dielectric layer below the continuous dielectric layer in direct contact with a side of the liner, wherein the shallow trench isolation region is below a source drain between the first nanosheet stack and the second nanosheet stack.
8 . The semiconductor device according to claim 7 , wherein a second continuous dielectric layer below the first nanosheet stack, below the second nanosheet stack and above the shallow trench isolation region.
9 . The semiconductor device according to claim 7 , further comprising:
a silicon dioxide (SiO 2 ) layer below the first nanosheet stack bonded to a second silicon dioxide (SiO 2 ) layer above the substrate.
10 . The semiconductor device according to claim 7 , further comprising:
an upper source drain region between the upper nanosheet stack of the first nanosheet stack and the upper nanosheet stack of the second nanosheet stack; and
a lower source drain region between the lower nanosheet stack of the first nanosheet stack and the lower nanosheet stack of the second nanosheet stack.
11 . The semiconductor device according to claim 10 , further comprising:
an interlayer dielectric physically separating the upper source drain region and the lower source drain region.