IP Library › Granted Patent US 12677455

Granted Patent B2

US 12677455 · App. 18/162,854 · Granted Jul 7, 2026

Transistor device having a gate setback from a gate dielectric

Inventors: Ta-Yuan Kung (New Taipei City, TW); Chen-Liang Chu (Hsin-Chu, TW); Chih-Wen Albert Yao (Hsinchu City, TW); Fei-Yun Chen (Hinchu, TW); Ming-Ta Lei (Hsin-Chu City, TW); Ruey-Hsin Liu (Hsin-Chu, TW); Yu-Chang Jong (Hsinchu City, TW)

Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.

H10D62/151 H10D30/0285 H10D30/601 H10D62/126 H10D64/111 H10D64/671 H10P50/00

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Quick Facts

Patent No.: US 12677455
App. No.: 18/162,854
Granted: Jul 7, 2026
Kind: B2

External Links

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Abstract

An integrated chip including a first source/drain region and a second source/drain region in a semiconductor substrate and laterally spaced apart along a top surface of the substrate. A gate dielectric layer is over the substrate and extends laterally between the first source/drain region and the second source/drain region. A thickness of the gate dielectric layer along a first sidewall of the gate dielectric layer is less than an average thickness of the gate dielectric layer. A trench isolation layer extends along gate dielectric layer. A first sidewall of the trench isolation layer extends along the first sidewall of the gate dielectric layer. A gate layer is directly over the gate dielectric layer and between the first source/drain region and the second source/drain region. A first sidewall of the gate layer is directly over the gate dielectric layer and laterally setback from the first sidewall of the gate dielectric layer.

Claims (48)

1 . A method for forming an integrated chip, the method comprising:

etching a semiconductor substrate to form a trench in the semiconductor substrate, wherein the trench is delimited by a first sidewall of the semiconductor substrate and a second sidewall of the semiconductor substrate, and wherein the trench surrounds an active region of the semiconductor substrate;

depositing a trench isolation layer in the trench, wherein a first sidewall of the trench isolation layer extends along the first sidewall of the semiconductor substrate and a second sidewall of the trench isolation layer extends along the second sidewall of the semiconductor substrate;

forming a first high voltage (HV) well region in the semiconductor substrate, the first HV well region having a first doping type;

forming a second HV well region in the semiconductor substrate beside the first HV well region, the second HV well region having a second doping type, different than the first doping type;

forming a gate dielectric layer over the first HV well region, over the second HV well region, and laterally between the first sidewall of the trench isolation layer and the second sidewall of the trench isolation layer, the gate dielectric layer having a first sidewall that extends along the first sidewall of the trench isolation layer and a second sidewall that extends along the second sidewall of the trench isolation layer, wherein a thickness of the gate dielectric layer along the first sidewall of the gate dielectric layer is less than an average thickness of the gate dielectric layer;

depositing a gate layer over the gate dielectric layer;

etching the gate layer so that a first sidewall of the gate layer is directly over the gate dielectric layer and laterally setback from the first sidewall of the gate dielectric layer;

forming a first source/drain region in the first HV well region, the first source/drain region having the second doping type;

forming a second source/drain region in the second HV well region, the second source/drain region having the second doping type; and

forming a metal field plate directly over the gate layer and coupled to the gate layer.

2 . The method of claim 1 , further comprising:

etching the semiconductor substrate between the first sidewall and the second sidewall of the trench isolation layer to form a recess in the semiconductor substrate before forming the first HV well region in the semiconductor substrate, wherein the gate dielectric layer is formed in the recess, and wherein the forming the gate dielectric layer comprises performing a thermal oxide growth process.

3 . The method of claim 1 , wherein the first source/drain region and the second source/drain region are laterally spaced apart in a first direction, wherein the first sidewall of the gate dielectric layer, the first sidewall of the trench isolation layer, and the first sidewall of the gate layer extend in the first direction, and wherein the first sidewall of the gate layer is laterally setback from the first sidewall of the gate dielectric layer in a second direction, different than the first direction.

4 . The method of claim 1 , wherein the metal field plate extends toward the second source/drain region beyond the gate layer and directly over the second HV well region.

5 . The method of claim 1 , wherein the metal field plate comprises a plurality of metal segments that extend in a first direction, are spaced apart in a second direction, and are connected by a connecting segment that extends in the second direction.

6 . The method of claim 1 , further comprising:

forming a body region having the first doping type in first HV well region, wherein the trench isolation layer separates the first source/drain region from the body region, and wherein the body region laterally surrounds the first source/drain region, the second source/drain region, and the trench isolation layer.

7 . A method for forming an integrated chip, the method comprising:

forming a trench isolation layer surrounding an active area of a semiconductor substrate;

etching the active area of the semiconductor substrate to form a gate dielectric recess in the active area of the semiconductor substrate, wherein the trench isolation layer surrounds the gate dielectric recess, and wherein a first sidewall of the trench isolation layer partially forms the gate dielectric recess;

forming a gate dielectric layer in the gate dielectric recess, wherein a first sidewall of the gate dielectric layer extends along the first sidewall of the trench isolation layer;

depositing a gate layer over the gate dielectric layer;

etching the gate layer to form a first sidewall of the gate layer, a bottom of the first sidewall of the gate layer being over a topmost surface of the gate dielectric layer and offset from the first sidewall of the gate dielectric layer; and

forming a first source/drain region and a second source/drain region in the semiconductor substrate, wherein the gate dielectric layer is laterally between the first source/drain region and the second source/drain region.

8 . The method of claim 7 , wherein a bottommost surface of of the gate layer is over the topmost surface of the gate dielectric layer.

9 . The method of claim 7 , further comprising:

forming a metal field plate over and coupled to the gate layer, wherein the metal field plate covers the gate layer when viewed in top view.

10 . The method of claim 9 , further comprising:

forming a plurality of contacts on and coupled to the gate layer, wherein the metal field plate is formed on and coupled to the plurality of contacts.

11 . The method of claim 7 , wherein the gate dielectric layer is formed in the gate dielectric recess by a thermal oxidation process.

12 . The method of claim 7 , wherein a distance between a top of the first sidewall of the gate dielectric layer and a bottom of the first sidewall of the gate dielectric layer is less than an average distance between the topmost surface of the gate dielectric layer and a bottom surface of the gate dielectric layer.

13 . The method of claim 7 , further comprising:

forming a first well region and a second well region in the semiconductor substrate, wherein the first and second source/drain regions are formed in the first and second well regions, respectively, and wherein the gate dielectric recess is formed in the first and second well regions.

14 . The method of claim 13 , wherein the first well region laterally surrounds the second well region.

15 . A method of forming an integrated chip, the method comprising:

forming a gate dielectric layer over a portion of a semiconductor substrate and laterally between a first source/drain region and a second source/drain region of the semiconductor substrate, wherein a thickness of the gate dielectric layer along a first sidewall of the gate dielectric layer is less than an average thickness of the gate dielectric layer;

forming a trench isolation layer surrounding the portion of the semiconductor substrate, wherein a first sidewall of the trench isolation layer extends along the first sidewall of the gate dielectric layer and a first sidewall of the semiconductor substrate; and

forming a gate layer on the gate dielectric layer and between the first source/drain region and the second source/drain region,

wherein an upper surface of the gate dielectric layer extends laterally from a top of the first sidewall of the gate dielectric layer to a bottom of a first sidewall of the gate layer, and wherein a top of the first sidewall of the semiconductor substrate is under a bottom of the first sidewall of the gate dielectric layer and over a bottommost surface of the gate dielectric layer.

16 . The method of claim 15 , further comprising:

forming a metal field plate over the gate layer, wherein a perimeter of the metal field plate surrounds a perimeter of the gate layer in top view.

17 . The method of claim 16 , wherein the metal field plate extends over the first sidewall of the gate layer, the first sidewall of the gate dielectric layer, and the first sidewall of the trench isolation layer.

18 . The method of claim 15 , wherein the first source/drain region extends along a second sidewall of the gate dielectric layer, and wherein the second source/drain region extends along a third sidewall of the gate dielectric layer.

19 . The method of claim 15 , further comprising:

forming the first source/drain region and the second source/drain region in the semiconductor substrate, wherein the first source/drain region and the second source/drain region extend along the first sidewall of the trench isolation layer.

20 . The method of claim 19 , further comprising:

forming a first well region and a second well region in the semiconductor substrate, wherein the first well region laterally surrounds the second well region, wherein the first source/drain region is formed in the first well region, wherein the second source/drain region is formed in the second well region, wherein the first well region has a first doping type, and wherein the second well region, the first source/drain region, and the second source/drain region have a second doping type different than the first doping type.