Integrating standard-gate transistors and extended-gate transistors on the same substrate using low-temperature gate dielectric treatments
Embodiments of the invention are directed to a method of fabricating an integrated circuit (IC). The method includes performing fabrication operations to form an extended-gate field effect transistor (EG-FET) on a substrate. The fabrication operations include forming a channel in an EG region of the substrate. A first EG gate dielectric is deposited over the channel at a first low-temperature. A reinforcement treatment is applied to the first EG gate dielectric at a second low-temperature, wherein the reinforcement treatment converts the first EG gate dielectric to a reinforced first EG gate dielectric. The first low-temperature is selected to be below the second low-temperature; and the second low-temperature is selected to be below a third low-temperature that causes a diffusion of a first type of semiconductor material across an interface and into a second type of semiconductor to exceed a predetermined minimum diffusion level or rate.
1 . A method of fabricating an integrated circuit (IC), the method comprising:
performing fabrication operations to form an extended-gate field effect transistor (EG-FET) and a standard gate FET (SG-FET) on a substrate, wherein the EG-FET provides a maximum extended gate (EG) threshold voltage, wherein the SG-FET provides a maximum standard gate (SG) threshold voltage that is less than the maximum EG threshold voltage, and wherein the fabrication operations include:
forming a channel in an EG region of the substrate;
depositing a first EG gate dielectric over the channel at a first low-temperature;
wherein the first EG gate dielectric comprises a first quality level, the first quality level being defined by a measurable property of the EG gate dielectric that is correlated with an ability of the EG-FET to provide the maximum EG threshold voltage; and
applying a reinforcement treatment to the first EG gate dielectric at a second low-temperature, wherein the reinforcement treatment converts the first EG gate dielectric to a reinforced first EG gate dielectric comprising a second quality level, the second quality level being defined by the measurable property and being correlated with an increased ability of the EG-FET to provide the maximum EG threshold voltage relative to the first quality level;
wherein the second quality level is greater than the first quality level.
2 . The method of claim 1 , wherein:
the first low-temperature is at or below about 400 degrees Celsius; and
the second low-temperatures is at or below about 800 degrees Celsius.
3 . The method of claim 1 , wherein:
the reinforcement treatment comprises a nitridation treatment; and
the reinforced first EG gate dielectric comprises a nitride.
4 . The method of claim 1 , wherein the fabrication operations further include:
selecting the first low-temperature to be below the second low-temperature; and
selecting the second low-temperature to be below a third low-temperature that causes a diffusion of a first type of semiconductor material across an interface and into a second type of semiconductor to exceed a predetermined minimum diffusion level.
5 . The method of claim 1 , wherein:
the reinforcement treatment comprises a plasma densification; and
the reinforced first EG gate dielectric includes reinforcement elements selected from the list consisting of argon, helium, and hydrogen.
6 . The method of claim 1 , wherein the fabrication operations further comprise:
depositing an SG gate dielectric over the reinforced first EG gate dielectric;
wherein the reinforced first EG gate dielectric comprises a first thickness;
wherein the SG gate dielectric comprises a second thickness; and
wherein the second thickness is less than the first thickness.
7 . The method of claim 6 , wherein the SG gate dielectric comprises a high-k dielectric layer.
8 . The method of claim 7 , wherein the SG gate dielectric further comprises an interfacial layer.
9 . The method of claim 6 further comprising depositing a second EG gate dielectric between the reinforced first EG gate dielectric and the SG gate dielectric, wherein the second EG gate dielectric comprise a third thickness.
10 . The method of claim 9 , wherein the second thickness is less than the third thickness.
11 . The method of claim 1 , wherein the EG-FET comprises a fin-type FET.
12 . A method of fabricating an integrated circuit (IC), the method comprising:
performing fabrication operations to form an extended-gate field effect transistor (EG-FET) and a standard-gate field effect transistor (SG-FET) on a substrate, wherein the EG-FET provides a maximum extended gate (EG) threshold voltage, wherein the SG-FET provides a maximum standard gate (SG) threshold voltage that is less than the maximum EG threshold voltage, and wherein the fabrication operations include:
forming a stack in an SG region of the substrate, wherein the stack comprises a layer of a first type of semiconductor material, a layer of a second type of semiconductor material, and an interface between the layer of the first type of semiconductor material and the layer of the second type of semiconductor material;
depositing an SG gate dielectric over the stack;
forming a channel in an EG region of the substrate;
depositing a first EG gate dielectric over the channel at a first low-temperature;
wherein the first EG gate dielectric comprises a first quality level, the first quality level being defined by a measurable property of the EG gate dielectric that is correlated with an ability of the EG-FET to provide the maximum EG threshold voltage;
applying a reinforcement treatment to the first EG gate dielectric at a second low-temperature, wherein the reinforcement treatment converts the first EG gate dielectric to a reinforced first EG gate dielectric comprising a second quality level, the second quality level being defined by the measurable property and being correlated with an increased ability of the EG-FET to provide the maximum EG threshold voltage relative to the first quality level;
wherein the second quality level is greater than the first quality level.
13 . The method of claim 12 , wherein:
the EG-FET comprises a fin-type FET;
the SG-FET comprises a nanosheet FET;
the first low-temperature is at or below about 400 degrees Celsius; and
the second low-temperatures is at or below about 800 degrees Celsius.
14 . The method of claim 12 , wherein:
the reinforcement treatment comprises a nitridation treatment; and
the reinforced first EG gate dielectric comprises a nitride.
15 . The method of claim 12 , wherein:
the reinforcement treatment comprises a plasma densification; and
the reinforced first EG gate dielectric includes reinforcement elements selected from the list consisting of argon, helium, and hydrogen.
16 . The method of claim 12 further comprising:
depositing the SG dielectric over the reinforced first EG gate dielectric;
wherein a thickness of the SG dielectric is less than a thickness of the reinforced first EG gate dielectric;
depositing a second EG gate dielectric between the reinforced first EG gate dielectric and the SG gate dielectric;
wherein the second EG gate dielectric comprise a second EG gate dielectric thickness; and
wherein the thickness of the SG gate dielectric is less than a thickness of the second EG gate dielectric.
17 . The method of claim 12 , wherein:
the fabrication operations further include:
selecting the first low-temperature to be below the second low-temperature;
selecting the second low-temperature to be below a third low-temperature that causes a diffusion of the first type of semiconductor material across the interface and into the second type of semiconductor to exceed a predetermined minimum diffusion level;
the EG-FET comprises a fin-type FET; and
the SG-FET comprises a nanosheet FET.