IP Library › Granted Patent US 12677464
Granted Patent B2
US 12677464 · App. 18/313,368 · Granted Jul 7, 2026

Semiconductor devices having vertical field effect transistors

Inventors: Yi-Yi Chen (Keelung City, TW); Chi-Yu Lu (New Taipei City, TW); Chih-Liang Chen (Hsinchu City, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
H10D64/252H10D30/025H10D30/63H10D84/0149H10D84/016H10D84/038H10D84/83
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12677464
App. No.
18/313,368
Granted
Jul 7, 2026
Kind
B2
Abstract

A semiconductor structure includes a first upper source/drain region, a second upper source/drain region, a first lower source/drain contact, a second lower source/drain contact, and a third conductive region. The first upper source/drain contact is disposed at a first elevation. The second upper source/drain contact is disposed at the first elevation. The first lower source/drain contact is disposed at a second elevation. The second lower source/drain contact is disposed at the second elevation. The third conductive region is disposed at a third elevation. A projection area of the third conductive region is disposed between a projection area of the first upper source/drain contact and a projection area of the second upper source/drain contact. The third elevation is disposed between the first elevation and the second elevation.

Claims (40)

1 . A semiconductor structure comprising:

a first upper source/drain contact disposed at a first elevation;

a second upper source/drain contact disposed at the first elevation;

a first lower source/drain contact disposed at a second elevation;

a second lower source/drain contact disposed at the second elevation; and

a third conductive region disposed at a third elevation, wherein a projection area of the third conductive region is disposed between a projection area of the first upper source/drain contact and a projection area of the second upper source/drain region, and wherein the third elevation is disposed between the first elevation and the second elevation.

2 . The semiconductor structure of claim 1 , further comprising a first vertical field effect transistor (VFET) structure, wherein the first VFET structure comprises the first upper source/drain contact and the first lower source/drain contact.

3 . The semiconductor structure of claim 2 , wherein the first VFET structure further comprises an active/doped region in contact with the first upper source/drain contact and the first lower source/drain contact.

4 . The semiconductor structure of claim 1 , wherein the projection area of the third conductive region is disposed between a projection area of the first lower source/drain contact and a projection area of the second lower source/drain contact.

5 . The semiconductor structure of claim 3 , further comprising a metal gate layer disposed at the third elevation, wherein the metal gate layer contacts the active/doped region and surrounds a portion of the active/doped region.

6 . The semiconductor structure of claim 5 , wherein the metal gate layer contacts and is electrically connected to the third conductive region.

7 . The semiconductor structure of claim 6 , further comprising a second VFET structure adjacent to the first VFET structure, wherein the second VFET structure comprises the second upper source/drain contact and the second lower source/drain contact, wherein the second VFET structure and the first VFET structure are in contact with the third conductive region.

8 . The semiconductor structure of claim 7 , further comprising a third VFET structure adjacent to the second VFET structure, wherein the second VFET structure and the third VFET structure are configured to be controlled by a fourth conductive region between the third VFET structure and the second VFET structure.

9 . The semiconductor structure of claim 1 , wherein the first upper source/drain contact overlaps with the first lower source/drain contact from a top view.

10 . The semiconductor structure of claim 1 , further comprising:

a second VFET structure adjacent to the first VFET structure, wherein the second VFET structure comprises a second upper source/drain contact;

a third VFET structure adjacent to the second VFET structure, wherein the third VFET structure comprises a third upper source/drain contact; and

a fourth VFET structure adjacent to the third VFET structure, wherein the fourth VFET structure comprises a fourth upper source/drain contact;

wherein the first upper source/drain contact contacts the second upper source/drain contact, wherein the second upper source/drain contact contacts the third upper source/drain contact, and wherein the third upper source/drain contact contacts the fourth upper source/drain contact from a top view.

11 . The semiconductor structure of claim 10 , wherein at least two of a first lateral width of the first upper source/drain contact, a second lateral width of the second upper source/drain contact, a third lateral width of the third upper source/drain contact, and a fourth lateral width of the fourth upper source/drain contact are different from each other from a top view.

12 . The semiconductor structure of claim 1 , further comprising a fifth conductive region and a sixth conductive region disposed at a fourth elevation above the first elevation, wherein two edges of the fifth conductive region are misaligned with two edges of the sixth conductive region.

13 . A semiconductor structure comprising:

a first VFET structure, wherein the first VFET structure comprises a first upper source/drain contact;

a second VFET structure adjacent to the first VFET structure, wherein the second VFET structure comprises a second upper source/drain contact; and

a third conductive region, wherein a projection area of the third conductive region is disposed between a projection area of the first upper source/drain contact and a projection area of the second upper source/drain contact, wherein an elevation of the third conductive region is disposed below an elevation of the first upper source/drain contact and the second upper source/drain contact, wherein the first VFET structure further comprises an active/doped region and a first lower source/drain contact, wherein the active/doped region contacts the first upper source/drain contact and the first lower source/drain contact, wherein a third elevation layer comprises a metal gate layer, wherein the metal gate layer contacts the active/doped region and surrounds a portion of the active/doped region.

14 . The semiconductor structure of claim 13 , wherein the first upper source/drain contact is disposed at a first elevation and the first lower source/drain contact is disposed at a second elevation, wherein the first upper source/drain contact overlaps with the first lower source/drain contact from a top view.

15 . The semiconductor structure of claim 14 , wherein the first VFET structure further comprises an oxide diffusion region in contact with the first upper source/drain contact and the first lower source/drain contact.

16 . The semiconductor structure of claim 15 , further comprising:

a third VFET structure adjacent to the second VFET structure, wherein the third VFET structure comprises a third upper source/drain contact; and

a fourth VFET structure adjacent to the third VFET structure, wherein the fourth VFET structure comprises a fourth upper source/drain contact;

wherein the first upper source/drain contact contacts the second upper source/drain contact, wherein the second upper source/drain contact contacts the third upper source/drain contact, and wherein the third upper source/drain contact contacts the fourth upper source/drain contact from a top view.

17 . A semiconductor structure comprising:

a first VFET structure, wherein the first VFET structure comprises a first upper source/drain contact;

a second VFET structure adjacent to the first VFET structure, wherein the second VFET structure comprises a second upper source/drain contact;

a third VFET structure adjacent to the second VFET structure, wherein the third VFET structure comprises a third upper source/drain contact;

a fourth VFET structure adjacent to the third VFET structure, wherein the fourth VFET structure comprises a fourth upper source/drain contact; and

wherein the first upper source/drain contact contacts the second upper source/drain contact, wherein the second upper source/drain contact contacts the third upper source/drain contact, and wherein the third upper source/drain contact contacts the fourth upper source/drain contact from a top view.

18 . The semiconductor structure of claim 17 , further comprising a third elevation layer, wherein an elevation of the third elevation layer is disposed below an elevation of the first upper source/drain contact.

19 . The semiconductor structure of claim 18 , wherein the third elevation layer comprises a third conductive region, wherein a projection area of the third conductive region is disposed between a projection area of the first upper source/drain contact and a projection area of the second upper source/drain contact.

20 . The semiconductor structure of claim 19 , wherein the first VFET structure comprises a first lower source/drain contact and an active/doped region, wherein the active/doped region contacts the first upper source/drain contact and the first lower source/drain contact.