IP Library › Granted Patent US 12677465
Granted Patent B2
US 12677465 · App. 18/542,956 · Granted Jul 7, 2026

Source/drain extension with spacer layers

Inventors: Minhaz Abedin (Albany, NY); Ruilong Xie (Niskayuna, NY); Tao Li (Slingerlands, NY); Julien Frougier (Albany, NY); Mohammad Hasanuzzaman (Niskayuna, NY)
Assignee: International Business Machines Corporation
H10D64/254H10D30/43H10D30/6735H10D30/6757H10D62/121H10D84/83H10W20/427
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Quick Facts
Patent No.
US 12677465
App. No.
18/542,956
Granted
Jul 7, 2026
Kind
B2
Abstract

A semiconductor structure includes a first nanosheet field-effect transistor device having a plurality of first nanosheet channel layers disposed on a substrate, a second nanosheet field-effect transistor device adjacent the first field-effect transistor nanosheet device, the second field-effect transistor nanosheet device having a plurality of second nanosheet channel layers disposed on the substrate, a first source/drain region disposed between opposing sidewalls of the plurality of first nanosheet channel layers and the plurality of second nanosheet channel layers and extending into the substrate, and source/drain sidewall spacers disposed on sidewalls of the first source/drain region extending into the substrate.

Claims (44)

1 . A semiconductor structure, comprising:

a first nanosheet field-effect transistor device comprising a plurality of first nanosheet channel layers disposed on a substrate;

a second nanosheet field-effect transistor device adjacent the first field-effect transistor nanosheet device, the second field-effect transistor nanosheet device comprising a plurality of second nanosheet channel layers disposed on the substrate;

a first source/drain region disposed between opposing sidewalls of the plurality of first nanosheet channel layers and the plurality of second nanosheet channel layers and extending into the substrate; and

source/drain sidewall spacers disposed on sidewalls of the first source/drain region extending into the substrate and an interlevel dielectric layer.

2 . The semiconductor structure according to claim 1 , wherein the substrate comprises a bulk silicon substrate.

3 . The semiconductor structure according to claim 2 , wherein the bulk silicon substrate comprises a first crystalline structure and the first source/drain region comprises a second crystalline structure matching the first crystalline structure.

4 . The semiconductor structure according to claim 1 , wherein the first source/drain region is an epitaxial grown first source/drain region.

5 . The semiconductor structure according to claim 1 , wherein the first source/drain region disposed between the opposing sidewalls of the plurality of first nanosheet channel layers and the plurality of second nanosheet channel layers comprises a first width and the first source/drain region extending into the substrate comprises a second width different than the first width.

6 . The semiconductor structure according to claim 1 , further comprising a backside contact placeholder layer disposed between a bottom surface of the first source/drain region and a top surface of the substrate.

7 . The semiconductor structure according to claim 1 , further comprising:

a frontside source/drain contact connecting the first source/drain region to a frontside back-end-of-the-line interconnect.

8 . The semiconductor structure according to claim 1 , further comprising:

a third nanosheet field-effect transistor device adjacent the second field-effect transistor nanosheet device, the third field-effect transistor nanosheet device comprising a plurality of third nanosheet channel layers disposed on the substrate;

a second source/drain region disposed between opposing sidewalls of the plurality of second nanosheet channel layers and the plurality of third nanosheet channel layers and extending into the substrate and a backside interlevel dielectric layer; and

a backside contact disposed on a portion of sidewalls and a bottom surface of the second source/drain region extending into the backside interlevel dielectric layer.

9 . The semiconductor structure according to claim 8 , wherein the second source/drain region disposed between the opposing sidewalls of the plurality of second nanosheet channel layers and the plurality of third nanosheet channel layers comprises a first width and the second source/drain region extending into the substrate and the backside interlevel dielectric layer comprises a second width different than the first width.

10 . A semiconductor structure, comprising:

a first nanosheet field-effect transistor device comprising a plurality of first nanosheet channel layers disposed on a backside interlevel dielectric layer;

a second nanosheet field-effect transistor device adjacent the first field-effect transistor nanosheet device, the second field-effect transistor nanosheet device comprising a plurality of second nanosheet channel layers disposed on the backside interlevel dielectric layer;

a first source/drain region disposed between opposing sidewalls of the plurality of first nanosheet channel layers and the plurality of second nanosheet channel layers and extending into the backside interlevel dielectric layer;

source/drain sidewall spacers disposed on a portion of sidewalls of the first source/drain region extending into the backside interlevel dielectric layer, wherein the source/drain sidewall spacers are separated from the second nanosheet field-effect transistor device by the backside interlevel dielectric layer; and

a backside contact disposed on remaining portions of the sidewalls below the source/drain sidewall spacers and a bottom surface of the first source/drain region extending into the backside interlevel dielectric layer.

11 . The semiconductor structure according to claim 10 , wherein the backside contact connects the first source/drain region to a backside interconnect.

12 . The semiconductor structure according to claim 10 , wherein the first source/drain region disposed between the opposing sidewalls of the plurality of first nanosheet channel layers and the plurality of second nanosheet channel layers comprises a first width and the first source/drain region extending into the backside interlevel dielectric layer comprises a second width different than the first width.

13 . The semiconductor structure according to claim 10 , further comprising:

a third nanosheet field-effect transistor device adjacent the second field-effect transistor nanosheet device, the third field-effect transistor nanosheet device comprising a plurality of third nanosheet channel layers disposed on the backside interlevel dielectric layer; and

a second source/drain region disposed between opposing sidewalls of the plurality of second nanosheet channel layers and the plurality of third nanosheet channel layers.

14 . The semiconductor structure according to claim 13 , further comprising:

a frontside source/drain contact connecting the second source/drain region to a frontside back-end-of-the-line interconnect.

15 . The semiconductor structure according to claim 13 , wherein the second source/drain region is further disposed on a flowable dielectric layer.

16 . The semiconductor structure according to claim 10 , wherein the first source/drain region further extends into a substrate disposed between the backside interlevel dielectric layer and the plurality of first nanosheet channel layers and the plurality of second nanosheet channel layers.

17 . An integrated circuit, comprising:

one or more semiconductor structures, wherein at least one of the one or more semiconductor structures comprises:

a first nanosheet field-effect transistor device comprising a plurality of first nanosheet channel layers disposed on a substrate;

a second nanosheet field-effect transistor device adjacent the first field-effect transistor nanosheet device, the second field-effect transistor nanosheet device comprising a plurality of second nanosheet channel layers disposed on the substrate;

a first source/drain region disposed between opposing sidewalls of the plurality of first nanosheet channel layers and the plurality of second nanosheet channel layers and extending into the substrate; and

source/drain sidewall spacers disposed on sidewalls of the first source/drain region extending into the substrate and an interlevel dielectric layer.

18 . The integrated circuit according to claim 17 , wherein the substrate comprises a bulk silicon substrate comprising a first crystalline structure and the first source/drain region comprises a second crystalline structure matching the first crystalline structure.

19 . The integrated circuit according to claim 17 , wherein the first source/drain region disposed between the opposing sidewalls of the plurality of first nanosheet channel layers and the plurality of second nanosheet channel layers comprises a first width and the first source/drain region extending into the substrate comprises a second width different than the first width.

20 . The integrated circuit according to claim 17 , further comprising:

a third nanosheet field-effect transistor device adjacent the second field-effect transistor nanosheet device, the third field-effect transistor nanosheet device comprising a plurality of third nanosheet channel layers disposed on the substrate;

a second source/drain region disposed between opposing sidewalls of the plurality of second nanosheet channel layers and the plurality of third nanosheet channel layers and extending into the substrate and a backside interlevel dielectric layer; and

a backside contact disposed on a portion of sidewalls and a bottom surface of the second source/drain region extending into the backside interlevel dielectric layer.